Commit d7ade5f2 authored by José Roberto de Souza's avatar José Roberto de Souza
Browse files

drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL 



MBUS_DBOX_B2B_TRANSACTIONS_MAX, MBUS_DBOX_B2B_TRANSACTIONS_DELAY and
MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN were being programmed with
zeros while specification has different default values for this
registers in display 12 and newer.

While at it also converting all MBUS_DBOX macros to use REG_* macros.

BSpec: 50343
BSpec: 20231
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220330155724.255226-1-jose.souza@intel.com
parent 1dedcdd0

drivers/gpu/drm/i915/display/intel_display.c

+10 −3
Original line number Diff line number Diff line
@@ -1830,13 +1830,20 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus) 
{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;

	u32 val;

	u32 val = 0;



	if (DISPLAY_VER(dev_priv) >= 12) {

		val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);

		val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);

		val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;

	}



	/* Wa_22010947358:adl-p */

	if (IS_ALDERLAKE_P(dev_priv))

		val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4);

		val |= joined_mbus ? MBUS_DBOX_A_CREDIT(6) :

				     MBUS_DBOX_A_CREDIT(4);

	else

		val = MBUS_DBOX_A_CREDIT(2);

		val |= MBUS_DBOX_A_CREDIT(2);



	if (DISPLAY_VER(dev_priv) >= 12) {

		val |= MBUS_DBOX_BW_CREDIT(2);

drivers/gpu/drm/i915/i915_reg.h

+15 −10
Original line number Diff line number Diff line
@@ -1103,12 +1103,17 @@ 
#define _PIPEB_MBUS_DBOX_CTL			0x7103C

#define PIPE_MBUS_DBOX_CTL(pipe)		_MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \

							   _PIPEB_MBUS_DBOX_CTL)

#define MBUS_DBOX_BW_CREDIT_MASK	(3 << 14)

#define MBUS_DBOX_BW_CREDIT(x)		((x) << 14)

#define MBUS_DBOX_B_CREDIT_MASK		(0x1F << 8)

#define MBUS_DBOX_B_CREDIT(x)		((x) << 8)

#define MBUS_DBOX_A_CREDIT_MASK		(0xF << 0)

#define MBUS_DBOX_A_CREDIT(x)		((x) << 0)

#define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK	REG_GENMASK(24, 20) /* tgl+ */

#define MBUS_DBOX_B2B_TRANSACTIONS_MAX(x)	REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK, x)

#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK	REG_GENMASK(19, 17) /* tgl+ */

#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY(x)	REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK, x)

#define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN	REG_BIT(16) /* tgl+ */

#define MBUS_DBOX_BW_CREDIT_MASK		REG_GENMASK(15, 14)

#define MBUS_DBOX_BW_CREDIT(x)			REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x)

#define MBUS_DBOX_B_CREDIT_MASK			REG_GENMASK(12, 8)

#define MBUS_DBOX_B_CREDIT(x)			REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x)

#define MBUS_DBOX_A_CREDIT_MASK			REG_GENMASK(3, 0)

#define MBUS_DBOX_A_CREDIT(x)			REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x)



#define MBUS_UBOX_CTL			_MMIO(0x4503C)

#define MBUS_BBOX_CTL_S1		_MMIO(0x45040)