Commit d8264edf authored by Mike Rapoport's avatar Mike Rapoport Committed by Greg Kroah-Hartman
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staging: sm750fb: use BIT macro for CRT_DISPLAY_CTRL single-bit fields 



Replace complex definition of CRT_DISPLAY_CTRL register fields with
BIT() macro and use open-coded implementation for register manipulation

Signed-off-by: default avatarMike Rapoport <mike.rapoport@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 0f23be70

drivers/staging/sm750fb/ddk750_display.c

+1 −1
Original line number Diff line number Diff line
@@ -155,7 +155,7 @@ void ddk750_setLogicalDispOut(disp_output_t output) 
		reg = PEEK32(CRT_DISPLAY_CTRL);

		reg = FIELD_VALUE(reg, CRT_DISPLAY_CTRL, SELECT, (output & CRT_2_MASK)>>CRT_2_OFFSET);

		/*se blank off */

		reg = FIELD_SET(reg, CRT_DISPLAY_CTRL, BLANK, OFF);

		reg &= ~CRT_DISPLAY_CTRL_BLANK;

		POKE32(CRT_DISPLAY_CTRL, reg);



	}

drivers/staging/sm750fb/ddk750_mode.c

+1 −2
Original line number Diff line number Diff line
@@ -61,8 +61,7 @@ static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam, 
	dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL25);



	/* Set bit 25:24 of display controller */

	dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CRTSELECT, CRT);

	dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, RGBBIT, 24BIT);

	dispControl |= (CRT_DISPLAY_CTRL_CRTSELECT | CRT_DISPLAY_CTRL_RGBBIT);



	/* Set bit 14 of display controller */

	dispControl = DISPLAY_CTRL_CLOCK_PHASE;

drivers/staging/sm750fb/ddk750_reg.h

+9 −30
Original line number Diff line number Diff line
@@ -1331,38 +1331,19 @@ 
#define CRT_DISPLAY_CTRL_CLK_PLL80                    5

#define CRT_DISPLAY_CTRL_CLK_PLL108                   6

#define CRT_DISPLAY_CTRL_CLK_RESERVED                 7

#define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC                26:26

#define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_DISABLE        1

#define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_ENABLE         0

#define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC                BIT(26)



/* SM750LE definition */

#define CRT_DISPLAY_CTRL_CRTSELECT                    25:25

#define CRT_DISPLAY_CTRL_CRTSELECT_VGA                0

#define CRT_DISPLAY_CTRL_CRTSELECT_CRT                1

#define CRT_DISPLAY_CTRL_RGBBIT                       24:24

#define CRT_DISPLAY_CTRL_RGBBIT_24BIT                 0

#define CRT_DISPLAY_CTRL_RGBBIT_12BIT                 1

#define CRT_DISPLAY_CTRL_CRTSELECT                    BIT(25)

#define CRT_DISPLAY_CTRL_RGBBIT                       BIT(24)



#ifndef VALIDATION_CHIP

    #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC            26:26

    #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_DISABLE    1

    #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_ENABLE     0

    #define CRT_DISPLAY_CTRL_CENTERING                24:24

    #define CRT_DISPLAY_CTRL_CENTERING_DISABLE        0

    #define CRT_DISPLAY_CTRL_CENTERING_ENABLE         1

    #define CRT_DISPLAY_CTRL_CENTERING                BIT(24)

#endif

#define CRT_DISPLAY_CTRL_LOCK_TIMING                  23:23

#define CRT_DISPLAY_CTRL_LOCK_TIMING_DISABLE          0

#define CRT_DISPLAY_CTRL_LOCK_TIMING_ENABLE           1

#define CRT_DISPLAY_CTRL_EXPANSION                    22:22

#define CRT_DISPLAY_CTRL_EXPANSION_DISABLE            0

#define CRT_DISPLAY_CTRL_EXPANSION_ENABLE             1

#define CRT_DISPLAY_CTRL_VERTICAL_MODE                21:21

#define CRT_DISPLAY_CTRL_VERTICAL_MODE_REPLICATE      0

#define CRT_DISPLAY_CTRL_VERTICAL_MODE_INTERPOLATE    1

#define CRT_DISPLAY_CTRL_HORIZONTAL_MODE              20:20

#define CRT_DISPLAY_CTRL_HORIZONTAL_MODE_REPLICATE    0

#define CRT_DISPLAY_CTRL_HORIZONTAL_MODE_INTERPOLATE  1

#define CRT_DISPLAY_CTRL_LOCK_TIMING                  BIT(23)

#define CRT_DISPLAY_CTRL_EXPANSION                    BIT(22)

#define CRT_DISPLAY_CTRL_VERTICAL_MODE                BIT(21)

#define CRT_DISPLAY_CTRL_HORIZONTAL_MODE              BIT(20)

#define CRT_DISPLAY_CTRL_SELECT                       19:18

#define CRT_DISPLAY_CTRL_SELECT_PANEL                 0

#define CRT_DISPLAY_CTRL_SELECT_VGA                   1
@@ -1372,9 +1353,7 @@ 
#define CRT_DISPLAY_CTRL_FIFO_3                       1

#define CRT_DISPLAY_CTRL_FIFO_7                       2

#define CRT_DISPLAY_CTRL_FIFO_11                      3

#define CRT_DISPLAY_CTRL_BLANK                        10:10

#define CRT_DISPLAY_CTRL_BLANK_OFF                    0

#define CRT_DISPLAY_CTRL_BLANK_ON                     1

#define CRT_DISPLAY_CTRL_BLANK                        BIT(10)

#define CRT_DISPLAY_CTRL_PIXEL                        7:4

#define CRT_DISPLAY_CTRL_FORMAT                       1:0

#define CRT_DISPLAY_CTRL_FORMAT_8                     0

drivers/staging/sm750fb/sm750_hw.c

+17 −12
Original line number Diff line number Diff line
@@ -378,31 +378,35 @@ int hw_sm750le_setBLANK(struct lynxfb_output *output, int blank) 
	switch (blank) {

	case FB_BLANK_UNBLANK:

		dpms = CRT_DISPLAY_CTRL_DPMS_0;

		crtdb = CRT_DISPLAY_CTRL_BLANK_OFF;

		crtdb = 0;

		break;

	case FB_BLANK_NORMAL:

		dpms = CRT_DISPLAY_CTRL_DPMS_0;

		crtdb = CRT_DISPLAY_CTRL_BLANK_ON;

		crtdb = CRT_DISPLAY_CTRL_BLANK;

		break;

	case FB_BLANK_VSYNC_SUSPEND:

		dpms = CRT_DISPLAY_CTRL_DPMS_2;

		crtdb = CRT_DISPLAY_CTRL_BLANK_ON;

		crtdb = CRT_DISPLAY_CTRL_BLANK;

		break;

	case FB_BLANK_HSYNC_SUSPEND:

		dpms = CRT_DISPLAY_CTRL_DPMS_1;

		crtdb = CRT_DISPLAY_CTRL_BLANK_ON;

		crtdb = CRT_DISPLAY_CTRL_BLANK;

		break;

	case FB_BLANK_POWERDOWN:

		dpms = CRT_DISPLAY_CTRL_DPMS_3;

		crtdb = CRT_DISPLAY_CTRL_BLANK_ON;

		crtdb = CRT_DISPLAY_CTRL_BLANK;

		break;

	default:

		return -EINVAL;

	}



	if (output->paths & sm750_crt) {

		unsigned int val;



		POKE32(CRT_DISPLAY_CTRL, FIELD_VALUE(PEEK32(CRT_DISPLAY_CTRL), CRT_DISPLAY_CTRL, DPMS, dpms));

		POKE32(CRT_DISPLAY_CTRL, FIELD_VALUE(PEEK32(CRT_DISPLAY_CTRL), CRT_DISPLAY_CTRL, BLANK, crtdb));



		val = PEEK32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_BLANK;

		POKE32(CRT_DISPLAY_CTRL, val | crtdb);

	}

	return 0;

}
@@ -418,24 +422,23 @@ int hw_sm750_setBLANK(struct lynxfb_output *output, int blank) 
		pr_debug("flag = FB_BLANK_UNBLANK\n");

		dpms = SYSTEM_CTRL_DPMS_VPHP;

		pps = PANEL_DISPLAY_CTRL_DATA;

		crtdb = CRT_DISPLAY_CTRL_BLANK_OFF;

		break;

	case FB_BLANK_NORMAL:

		pr_debug("flag = FB_BLANK_NORMAL\n");

		dpms = SYSTEM_CTRL_DPMS_VPHP;

		crtdb = CRT_DISPLAY_CTRL_BLANK_ON;

		crtdb = CRT_DISPLAY_CTRL_BLANK;

		break;

	case FB_BLANK_VSYNC_SUSPEND:

		dpms = SYSTEM_CTRL_DPMS_VNHP;

		crtdb = CRT_DISPLAY_CTRL_BLANK_ON;

		crtdb = CRT_DISPLAY_CTRL_BLANK;

		break;

	case FB_BLANK_HSYNC_SUSPEND:

		dpms = SYSTEM_CTRL_DPMS_VPHN;

		crtdb = CRT_DISPLAY_CTRL_BLANK_ON;

		crtdb = CRT_DISPLAY_CTRL_BLANK;

		break;

	case FB_BLANK_POWERDOWN:

		dpms = SYSTEM_CTRL_DPMS_VNHN;

		crtdb = CRT_DISPLAY_CTRL_BLANK_ON;

		crtdb = CRT_DISPLAY_CTRL_BLANK;

		break;

	}
@@ -443,7 +446,9 @@ int hw_sm750_setBLANK(struct lynxfb_output *output, int blank) 
		unsigned int val = PEEK32(SYSTEM_CTRL) & ~SYSTEM_CTRL_DPMS_MASK;



		POKE32(SYSTEM_CTRL, val | dpms);

		POKE32(CRT_DISPLAY_CTRL, FIELD_VALUE(PEEK32(CRT_DISPLAY_CTRL), CRT_DISPLAY_CTRL, BLANK, crtdb));



		val = PEEK32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_BLANK;

		POKE32(CRT_DISPLAY_CTRL, val | crtdb);

	}



	if (output->paths & sm750_panel) {