Commit d92a4a27 authored by Jernej Skrabec's avatar Jernej Skrabec Committed by Mauro Carvalho Chehab
Browse files

media: cedrus: hevc: Add support for multiple slices 



Now that segment address is available, support for multi-slice frames
can be easily added.

Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent 229e5bdc

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

+16 −10
Original line number Diff line number Diff line
@@ -247,6 +247,8 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, 
	const struct v4l2_ctrl_hevc_slice_params *slice_params;

	const struct v4l2_ctrl_hevc_decode_params *decode_params;

	const struct v4l2_hevc_pred_weight_table *pred_weight_table;

	unsigned int width_in_ctb_luma, ctb_size_luma;

	unsigned int log2_max_luma_coding_block_size;

	dma_addr_t src_buf_addr;

	dma_addr_t src_buf_end_addr;

	u32 chroma_log2_weight_denom;
@@ -260,15 +262,17 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, 
	decode_params = run->h265.decode_params;

	pred_weight_table = &slice_params->pred_weight_table;



	log2_max_luma_coding_block_size =

		sps->log2_min_luma_coding_block_size_minus3 + 3 +

		sps->log2_diff_max_min_luma_coding_block_size;

	ctb_size_luma = 1UL << log2_max_luma_coding_block_size;

	width_in_ctb_luma =

		DIV_ROUND_UP(sps->pic_width_in_luma_samples, ctb_size_luma);



	/* MV column buffer size and allocation. */

	if (!ctx->codec.h265.mv_col_buf_size) {

		unsigned int num_buffers =

			run->dst->vb2_buf.vb2_queue->num_buffers;

		unsigned int log2_max_luma_coding_block_size =

			sps->log2_min_luma_coding_block_size_minus3 + 3 +

			sps->log2_diff_max_min_luma_coding_block_size;

		unsigned int ctb_size_luma =

			1UL << log2_max_luma_coding_block_size;



		/*

		 * Each CTB requires a MV col buffer with a specific unit size.
@@ -322,14 +326,16 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, 
	reg = VE_DEC_H265_BITS_END_ADDR_BASE(src_buf_end_addr);

	cedrus_write(dev, VE_DEC_H265_BITS_END_ADDR, reg);



	/* Coding tree block address: start at the beginning. */

	reg = VE_DEC_H265_DEC_CTB_ADDR_X(0) | VE_DEC_H265_DEC_CTB_ADDR_Y(0);

	/* Coding tree block address */

	reg = VE_DEC_H265_DEC_CTB_ADDR_X(slice_params->slice_segment_addr % width_in_ctb_luma);

	reg |= VE_DEC_H265_DEC_CTB_ADDR_Y(slice_params->slice_segment_addr / width_in_ctb_luma);

	cedrus_write(dev, VE_DEC_H265_DEC_CTB_ADDR, reg);



	cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, 0);

	cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, 0);



	/* Clear the number of correctly-decoded coding tree blocks. */

	if (ctx->fh.m2m_ctx->new_frame)

		cedrus_write(dev, VE_DEC_H265_DEC_CTB_NUM, 0);



	/* Initialize bitstream access. */
@@ -482,7 +488,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, 
				V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT,

				slice_params->flags);



	/* FIXME: For multi-slice support. */

	if (ctx->fh.m2m_ctx->new_frame)

		reg |= VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_FIRST_SLICE_SEGMENT_IN_PIC;



	cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO0, reg);

drivers/staging/media/sunxi/cedrus/cedrus_video.c

+1 −0
Original line number Diff line number Diff line
@@ -340,6 +340,7 @@ static int cedrus_s_fmt_vid_out(struct file *file, void *priv, 


	switch (ctx->src_fmt.pixelformat) {

	case V4L2_PIX_FMT_H264_SLICE:

	case V4L2_PIX_FMT_HEVC_SLICE:

		vq->subsystem_flags |=

			VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF;

		break;