Commit d992fe53 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'soc-fixes-5.14-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 

Pull ARM SoC fixes from Arnd Bergmann:
 "Not much to see here. Half the fixes this time are for Qualcomm dts
  files, fixing small mistakes on certain machines. The other fixes are:

   - A 5.13 regression fix for freescale QE interrupt controller\

   - A fix for TI OMAP gpt12 timer error handling

   - A randconfig build regression fix for ixp4xx

   - Another defconfig fix following the CONFIG_FB dependency rework"

* tag 'soc-fixes-5.14-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  soc: fsl: qe: fix static checker warning
  ARM: ixp4xx: fix building both pci drivers
  ARM: configs: Update the nhk8815_defconfig
  bus: ti-sysc: Fix error handling for sysc_check_active_timer()
  soc: fsl: qe: convert QE interrupt controller to platform_device
  arm64: dts: qcom: sdm845-oneplus: fix reserved-mem
  arm64: dts: qcom: msm8994-angler: Disable cont_splash_mem
  arm64: dts: qcom: sc7280: Fixup cpufreq domain info for cpu7
  arm64: dts: qcom: msm8992-bullhead: Fix cont_splash_mem mapping
  arm64: dts: qcom: msm8992-bullhead: Remove PSCI
  arm64: dts: qcom: c630: fix correct powerdown pin for WSA881x
parents f87d6431 1e16a402

arch/arm/configs/nhk8815_defconfig

+3 −5
Original line number Diff line number Diff line
@@ -15,8 +15,6 @@ CONFIG_SLAB=y 
CONFIG_ARCH_NOMADIK=y

CONFIG_MACH_NOMADIK_8815NHK=y

CONFIG_AEABI=y

CONFIG_ZBOOT_ROM_TEXT=0x0

CONFIG_ZBOOT_ROM_BSS=0x0

CONFIG_MODULES=y

CONFIG_MODULE_UNLOAD=y

# CONFIG_BLK_DEV_BSG is not set
@@ -52,9 +50,9 @@ CONFIG_MTD_BLOCK=y 
CONFIG_MTD_ONENAND=y

CONFIG_MTD_ONENAND_VERIFY_WRITE=y

CONFIG_MTD_ONENAND_GENERIC=y

CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC=y

CONFIG_MTD_RAW_NAND=y

CONFIG_MTD_NAND_FSMC=y

CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC=y

CONFIG_BLK_DEV_LOOP=y

CONFIG_BLK_DEV_CRYPTOLOOP=y

CONFIG_BLK_DEV_RAM=y
@@ -97,6 +95,7 @@ CONFIG_REGULATOR=y 
CONFIG_DRM=y

CONFIG_DRM_PANEL_TPO_TPG110=y

CONFIG_DRM_PL111=y

CONFIG_FB=y

CONFIG_BACKLIGHT_CLASS_DEVICE=y

CONFIG_BACKLIGHT_PWM=y

CONFIG_FRAMEBUFFER_CONSOLE=y
@@ -136,9 +135,8 @@ CONFIG_NLS_ISO8859_15=y 
CONFIG_CRYPTO_MD5=y

CONFIG_CRYPTO_SHA1=y

CONFIG_CRYPTO_DES=y

# CONFIG_DEBUG_BUGVERBOSE is not set

CONFIG_DEBUG_INFO=y

# CONFIG_ENABLE_MUST_CHECK is not set

CONFIG_DEBUG_FS=y

# CONFIG_SCHED_DEBUG is not set

# CONFIG_DEBUG_PREEMPT is not set
 
# CONFIG_DEBUG_BUGVERBOSE is not set

arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h

+24 −24
Original line number Diff line number Diff line
@@ -218,30 +218,30 @@ 
/*

 * PCI Control/Status Registers

 */

#define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))



#define PCI_NP_AD               IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)

#define PCI_NP_CBE              IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)

#define PCI_NP_WDATA            IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)

#define PCI_NP_RDATA            IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)

#define PCI_CRP_AD_CBE          IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)

#define PCI_CRP_WDATA           IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)

#define PCI_CRP_RDATA           IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)

#define PCI_CSR                 IXP4XX_PCI_CSR(PCI_CSR_OFFSET) 

#define PCI_ISR                 IXP4XX_PCI_CSR(PCI_ISR_OFFSET)

#define PCI_INTEN               IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)

#define PCI_DMACTRL             IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)

#define PCI_AHBMEMBASE          IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)

#define PCI_AHBIOBASE           IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)

#define PCI_PCIMEMBASE          IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)

#define PCI_AHBDOORBELL         IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)

#define PCI_PCIDOORBELL         IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)

#define PCI_ATPDMA0_AHBADDR     IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)

#define PCI_ATPDMA0_PCIADDR     IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)

#define PCI_ATPDMA0_LENADDR     IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)

#define PCI_ATPDMA1_AHBADDR     IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)

#define PCI_ATPDMA1_PCIADDR     IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)

#define PCI_ATPDMA1_LENADDR     IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)

#define _IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))



#define PCI_NP_AD               _IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)

#define PCI_NP_CBE              _IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)

#define PCI_NP_WDATA            _IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)

#define PCI_NP_RDATA            _IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)

#define PCI_CRP_AD_CBE          _IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)

#define PCI_CRP_WDATA           _IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)

#define PCI_CRP_RDATA           _IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)

#define PCI_CSR                 _IXP4XX_PCI_CSR(PCI_CSR_OFFSET) 

#define PCI_ISR                 _IXP4XX_PCI_CSR(PCI_ISR_OFFSET)

#define PCI_INTEN               _IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)

#define PCI_DMACTRL             _IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)

#define PCI_AHBMEMBASE          _IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)

#define PCI_AHBIOBASE           _IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)

#define PCI_PCIMEMBASE          _IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)

#define PCI_AHBDOORBELL         _IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)

#define PCI_PCIDOORBELL         _IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)

#define PCI_ATPDMA0_AHBADDR     _IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)

#define PCI_ATPDMA0_PCIADDR     _IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)

#define PCI_ATPDMA0_LENADDR     _IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)

#define PCI_ATPDMA1_AHBADDR     _IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)

#define PCI_ATPDMA1_PCIADDR     _IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)

#define PCI_ATPDMA1_LENADDR     _IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)



/*

 * PCI register values and bit definitions

arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts

+12 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/* Copyright (c) 2015, LGE Inc. All rights reserved.

 * Copyright (c) 2016, The Linux Foundation. All rights reserved.

 * Copyright (c) 2021, Petr Vorel <petr.vorel@gmail.com>

 */



/dts-v1/;
@@ -9,6 +10,9 @@ 
#include "pm8994.dtsi"

#include "pmi8994.dtsi"



/* cont_splash_mem has different memory mapping */

/delete-node/ &cont_splash_mem;



/ {

	model = "LG Nexus 5X";

	compatible = "lg,bullhead", "qcom,msm8992";
@@ -17,6 +21,9 @@ / { 
	qcom,board-id = <0xb64 0>;

	qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;



	/* Bullhead firmware doesn't support PSCI */

	/delete-node/ psci;



	aliases {

		serial0 = &blsp1_uart2;

	};
@@ -38,6 +45,11 @@ ramoops@1ff00000 { 
			ftrace-size = <0x10000>;

			pmsg-size = <0x20000>;

		};



		cont_splash_mem: memory@3400000 {

			reg = <0 0x03400000 0 0x1200000>;

			no-map;

		};

	};

};

arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts

+4 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/* Copyright (c) 2015, Huawei Inc. All rights reserved.

 * Copyright (c) 2016, The Linux Foundation. All rights reserved.

 * Copyright (c) 2021, Petr Vorel <petr.vorel@gmail.com>

 */



/dts-v1/;



#include "msm8994.dtsi"



/* Angler's firmware does not report where the memory is allocated */

/delete-node/ &cont_splash_mem;



/ {

	model = "Huawei Nexus 6P";

	compatible = "huawei,angler", "qcom,msm8994";

arch/arm64/boot/dts/qcom/sc7280.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -200,7 +200,7 @@ CPU7: cpu@700 { 
					   &BIG_CPU_SLEEP_1

					   &CLUSTER_SLEEP_0>;

			next-level-cache = <&L2_700>;

			qcom,freq-domain = <&cpufreq_hw 1>;

			qcom,freq-domain = <&cpufreq_hw 2>;

			#cooling-cells = <2>;

			L2_700: l2-cache {

				compatible = "cache";