Commit d9d86d08 authored by Horace Chen's avatar Horace Chen Committed by Alex Deucher
Browse files

drm/amdgpu: refine virtualization psp fw skip check 



SR-IOV may need to load different firmwares for different ASIC inside
VF.
So create a new function in amdgpu_virt to check whether FW load needs
to be skipped.

Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarHorace Chen <horace.chen@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent afb50906

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+3 −14
Original line number Diff line number Diff line
@@ -340,11 +340,12 @@ static int psp_init_sriov_microcode(struct psp_context *psp) 
		ret = psp_init_cap_microcode(psp, "aldebaran");

		ret &= psp_init_ta_microcode(psp, "aldebaran");

		break;

	case IP_VERSION(13, 0, 0):

		break;

	default:

		BUG();

		break;

	}



	return ret;

}
@@ -2412,19 +2413,7 @@ static bool fw_load_skip_check(struct psp_context *psp, 
		return true;



	if (amdgpu_sriov_vf(psp->adev) &&

	   (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0

	    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1

	    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2

	    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3

	    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4

	    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5

	    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6

	    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7

	    || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G

	    || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL

	    || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM

	    || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM

	    || ucode->ucode_id == AMDGPU_UCODE_ID_SMC))

	    amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))

		/*skip ucode loading in SRIOV VF */

		return true;

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

+29 −0
Original line number Diff line number Diff line
@@ -809,6 +809,35 @@ enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *ad 
	return mode;

}



bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id)

{

	/* this version doesn't support sriov autoload */

	if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 0)) {

		if (ucode_id == AMDGPU_UCODE_ID_VCN1 ||

		    ucode_id == AMDGPU_UCODE_ID_VCN)

			return false;

		else

			return true;

	}



	if (ucode_id == AMDGPU_UCODE_ID_SDMA0

	    || ucode_id == AMDGPU_UCODE_ID_SDMA1

	    || ucode_id == AMDGPU_UCODE_ID_SDMA2

	    || ucode_id == AMDGPU_UCODE_ID_SDMA3

	    || ucode_id == AMDGPU_UCODE_ID_SDMA4

	    || ucode_id == AMDGPU_UCODE_ID_SDMA5

	    || ucode_id == AMDGPU_UCODE_ID_SDMA6

	    || ucode_id == AMDGPU_UCODE_ID_SDMA7

	    || ucode_id == AMDGPU_UCODE_ID_RLC_G

	    || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL

	    || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM

	    || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM

	    || ucode_id == AMDGPU_UCODE_ID_SMC)

		return true;



	return false;

}



void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,

			struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,

			struct amdgpu_video_codec_info *decode, uint32_t decode_array_size)

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h

+2 −0
Original line number Diff line number Diff line
@@ -343,4 +343,6 @@ void amdgpu_sriov_wreg(struct amdgpu_device *adev, 
		       u32 acc_flags, u32 hwip);

u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,

		      u32 offset, u32 acc_flags, u32 hwip);

bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev,

			uint32_t ucode_id);

#endif