Commit da61731d authored by Aswath Govindraju's avatar Aswath Govindraju Committed by Vignesh Raghavendra
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arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0 



Configure first lane to PCIe, the second lane to USB and the last two lanes
to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is
connected to PCIe.

Signed-off-by: default avatarAswath Govindraju <a-govindraju@ti.com>
Signed-off-by: default avatarMatt Ranostay <mranostay@ti.com>
Signed-off-by: default avatarRavi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: default avatarRoger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230331090028.8373-5-r-gunasekaran@ti.com


Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
parent 80cfbf2f

arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts

+23 −0
Original line number Diff line number Diff line
@@ -9,6 +9,9 @@ 


#include "k3-j721s2-som-p0.dtsi"

#include <dt-bindings/net/ti-dp83867.h>

#include <dt-bindings/phy/phy-cadence.h>

#include <dt-bindings/phy/phy.h>

#include <dt-bindings/mux/ti-serdes.h>



/ {

	compatible = "ti,j721s2-evm", "ti,j721s2";
@@ -321,6 +324,26 @@ &cpsw_port1 { 
	phy-handle = <&phy0>;

};



&serdes_ln_ctrl {

	idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>,

		      <J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>;

};



&serdes_refclk {

	clock-frequency = <100000000>;

};



&serdes0 {

	status = "okay";

	serdes0_pcie_link: phy@0 {

		reg = <0>;

		cdns,num-lanes = <1>;

		#phy-cells = <0>;

		cdns,phy-type = <PHY_TYPE_PCIE>;

		resets = <&serdes_wiz0 1>;

	};

};



&mcu_mcan0 {

	status = "okay";

	pinctrl-names = "default";