Commit da8d1a35 authored by Thierry Reding's avatar Thierry Reding
Browse files

clk: tegra: Rename sor0_lvds to sor0_out 



This makes Tegra124 and Tegra210 consistent with subsequent Tegra
generations.

Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent e5f8a107

drivers/clk/tegra/clk-id.h

+1 −1
Original line number Diff line number Diff line
@@ -236,7 +236,7 @@ enum clk_id { 
	tegra_clk_soc_therm,

	tegra_clk_soc_therm_8,

	tegra_clk_sor0,

	tegra_clk_sor0_lvds,

	tegra_clk_sor0_out,

	tegra_clk_sor1,

	tegra_clk_sor1_out,

	tegra_clk_spdif,

drivers/clk/tegra/clk-tegra124.c

+6 −6
Original line number Diff line number Diff line
@@ -847,7 +847,7 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = { 
	[tegra_clk_adx1] = { .dt_id = TEGRA124_CLK_ADX1, .present = true },

	[tegra_clk_dpaux] = { .dt_id = TEGRA124_CLK_DPAUX, .present = true },

	[tegra_clk_sor0] = { .dt_id = TEGRA124_CLK_SOR0, .present = true },

	[tegra_clk_sor0_lvds] = { .dt_id = TEGRA124_CLK_SOR0_LVDS, .present = true },

	[tegra_clk_sor0_out] = { .dt_id = TEGRA124_CLK_SOR0_OUT, .present = true },

	[tegra_clk_gpu] = { .dt_id = TEGRA124_CLK_GPU, .present = true },

	[tegra_clk_amx1] = { .dt_id = TEGRA124_CLK_AMX1, .present = true },

	[tegra_clk_uartb] = { .dt_id = TEGRA124_CLK_UARTB, .present = true },
@@ -1011,14 +1011,14 @@ static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = { 
};

#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL



static const char *mux_clkm_plldp_sor0lvds[] = {

	"clk_m", "pll_dp", "sor0_lvds",

static const char *mux_clkm_plldp_sor0out[] = {

	"clk_m", "pll_dp", "sor0_out",

};

#define mux_clkm_plldp_sor0lvds_idx NULL

#define mux_clkm_plldp_sor0out_idx NULL



static struct tegra_periph_init_data tegra124_periph[] = {

	MUX8_NOGATE_LOCK("sor0_lvds", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_SOR0, tegra_clk_sor0_lvds, &sor0_lock),

	NODIV("sor0", mux_clkm_plldp_sor0lvds, CLK_SOURCE_SOR0, 14, 3, 182, 0, tegra_clk_sor0, &sor0_lock),

	MUX8_NOGATE_LOCK("sor0_out", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_SOR0, tegra_clk_sor0_out, &sor0_lock),

	NODIV("sor0", mux_clkm_plldp_sor0out, CLK_SOURCE_SOR0, 14, 3, 182, 0, tegra_clk_sor0, &sor0_lock),

};



static struct clk **clks;

drivers/clk/tegra/clk-tegra210.c

+1 −1
Original line number Diff line number Diff line
@@ -2351,7 +2351,7 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { 
	[tegra_clk_dpaux] = { .dt_id = TEGRA210_CLK_DPAUX, .present = true },

	[tegra_clk_dpaux1] = { .dt_id = TEGRA210_CLK_DPAUX1, .present = true },

	[tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true },

	[tegra_clk_sor0_lvds] = { .dt_id = TEGRA210_CLK_SOR0_LVDS, .present = true },

	[tegra_clk_sor0_out] = { .dt_id = TEGRA210_CLK_SOR0_OUT, .present = true },

	[tegra_clk_sor1] = { .dt_id = TEGRA210_CLK_SOR1, .present = true },

	[tegra_clk_sor1_out] = { .dt_id = TEGRA210_CLK_SOR1_OUT, .present = true },

	[tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true },