Commit db5b5c67 authored by Andrey Grodzovsky's avatar Andrey Grodzovsky Committed by Alex Deucher
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drm/amd/pm: Add STB support in sienna_cichlid 



Add STB implementation for sienna_cichlid

Signed-off-by: default avatarAndrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarLuben Tuikov <luben.tuikov@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 79aae67e

drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_offset.h

+7 −0
Original line number Diff line number Diff line
@@ -354,5 +354,12 @@ 
#define mmMP1_SMN_EXT_SCRATCH7                                                                         0x03c7

#define mmMP1_SMN_EXT_SCRATCH7_BASE_IDX                                                                0



/*

 * addressBlock: mp_SmuMp1Pub_MmuDec

 * base address: 0x0

 */

#define smnMP1_PMI_3_START                                                                              0x3030204

#define smnMP1_PMI_3_FIFO                                                                               0x3030208

#define smnMP1_PMI_3                                                                                    0x3030600



#endif

drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_sh_mask.h

+12 −0
Original line number Diff line number Diff line
@@ -959,5 +959,17 @@ 
#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT                                                                     0x0

#define MP1_SMN_EXT_SCRATCH7__DATA_MASK                                                                       0xFFFFFFFFL



// MP1_PMI_3_START

#define MP1_PMI_3_START__ENABLE_MASK                       0x80000000L

// MP1_PMI_3_FIFO

#define MP1_PMI_3_FIFO__DEPTH_MASK                         0x00000fffL



// MP1_PMI_3_START

#define MP1_PMI_3_START__ENABLE__SHIFT                     0x0000001f

// MP1_PMI_3_FIFO

#define MP1_PMI_3_FIFO__DEPTH__SHIFT                       0x00000000









#endif

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

+55 −0
Original line number Diff line number Diff line
@@ -80,6 +80,9 @@ 
		(*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\

} while(0)



/* STB FIFO depth is in 64bit units */

#define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8



static int get_table_size(struct smu_context *smu)

{

	if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
@@ -650,6 +653,8 @@ static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu) 
	return 0;

}



static void sienna_cichlid_stb_init(struct smu_context *smu);



static int sienna_cichlid_init_smc_tables(struct smu_context *smu)

{

	int ret = 0;
@@ -662,6 +667,8 @@ static int sienna_cichlid_init_smc_tables(struct smu_context *smu) 
	if (ret)

		return ret;



	sienna_cichlid_stb_init(smu);



	return smu_v11_0_init_smc_tables(smu);

}
@@ -3793,6 +3800,53 @@ static int sienna_cichlid_set_mp1_state(struct smu_context *smu, 
	return ret;

}



static void sienna_cichlid_stb_init(struct smu_context *smu)

{

	struct amdgpu_device *adev = smu->adev;

	uint32_t reg;



	reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START);

	smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE);



	/* STB is disabled */

	if (!smu->stb_context.enabled)

		return;



	spin_lock_init(&smu->stb_context.lock);



	/* STB buffer size in bytes as function of FIFO depth */

	reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO);

	smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH);

	smu->stb_context.stb_buf_size *=  SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES;



	dev_info(smu->adev->dev, "STB initialized to %d entries",

		 smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES);



}



int sienna_cichlid_stb_get_data_direct(struct smu_context *smu,

				       void *buf,

				       uint32_t size)

{

	uint32_t *p = buf;

	struct amdgpu_device *adev = smu->adev;



	/* No need to disable interrupts for now as we don't lock it yet from ISR */

	spin_lock(&smu->stb_context.lock);



	/*

	 * Read the STB FIFO in units of 32bit since this is the accessor window

	 * (register width) we have.

	 */

	buf = ((char *) buf) + size;

	while ((void *)p < buf)

		*p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3));



	spin_unlock(&smu->stb_context.lock);



	return 0;

}



static const struct pptable_funcs sienna_cichlid_ppt_funcs = {

	.get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,

	.set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
@@ -3882,6 +3936,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = { 
	.interrupt_work = smu_v11_0_interrupt_work,

	.gpo_control = sienna_cichlid_gpo_control,

	.set_mp1_state = sienna_cichlid_set_mp1_state,

	.stb_collect_info = sienna_cichlid_stb_get_data_direct,

};



void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)