Commit dbc1fdcb authored by Mauro Carvalho Chehab's avatar Mauro Carvalho Chehab
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Merge tag 'br-v6.2b' of git://linuxtv.org/hverkuil/media_tree into media_stage 

Tag branch

* tag 'br-v6.2b' of git://linuxtv.org/hverkuil/media_tree: (24 commits)
  media: imx-jpeg: Lock on ioctl encoder/decoder stop cmd
  media: imx-jpeg: Support contiguous and non contiguous format
  media: imx-jpeg: Implement g_selection and s_selection
  mtk-jpegdec: add stop cmd interface for jpgdec
  media: mtk-jpegdec: refactor jpegdec func interface
  media: mtk-jpegdec: add output pic reorder interface
  media: mtk-jpegdec: add jpeg decode worker interface
  media: mtk-jpegdec: add jpegdec timeout func interface
  media: mtk-jpegdec: support jpegdec multi-hardware
  media: mtk-jpegdec: export jpeg decoder functions
  dt-bindings: mediatek: Add mediatek,mt8195-jpgdec compatible
  mtk-jpegenc: add stop cmd interface for jpgenc
  mtk-jpegenc: add output pic reorder interface
  mtk-jpegenc: add jpeg encode worker interface
  mtk-jpegenc: add jpegenc timeout func interface
  mtk-jpegenc: support jpegenc multi-hardware
  mtk-jpegenc: export jpeg encoder functions
  dt-bindings: mediatek: Add mediatek, mt8195-jpgenc compatible
  media: imx-jpeg: Disable useless interrupt to avoid kernel panic
  media: imx-jpeg: Don't clear stop state in handling dynamic resolution change
  ...
parents e0eee57e df71c6e4

Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegdec.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek JPEG Decoder



maintainers:

  - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com>



description:

  MediaTek JPEG Decoder is the JPEG decode hardware present in MediaTek SoCs



properties:

  compatible:

    const: mediatek,mt8195-jpgdec



  power-domains:

    maxItems: 1



  iommus:

    maxItems: 6

    description:

      Points to the respective IOMMU block with master port as argument, see

      Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.

      Ports are according to the HW.



  dma-ranges:

    maxItems: 1

    description: |

      Describes the physical address space of IOMMU maps to memory.



  "#address-cells":

    const: 2



  "#size-cells":

    const: 2



  ranges: true



# Required child node:

patternProperties:

  "^jpgdec@[0-9a-f]+$":

    type: object

    description:

      The jpeg decoder hardware device node which should be added as subnodes to

      the main jpeg node.



    properties:

      compatible:

        const: mediatek,mt8195-jpgdec-hw



      reg:

        maxItems: 1



      iommus:

        minItems: 1

        maxItems: 32

        description:

          List of the hardware port in respective IOMMU block for current Socs.

          Refer to bindings/iommu/mediatek,iommu.yaml.



      interrupts:

        maxItems: 1



      clocks:

        maxItems: 1



      clock-names:

        items:

          - const: jpgdec



      power-domains:

        maxItems: 1



    required:

      - compatible

      - reg

      - iommus

      - interrupts

      - clocks

      - clock-names

      - power-domains



    additionalProperties: false



required:

  - compatible

  - power-domains

  - iommus

  - dma-ranges

  - ranges



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/memory/mt8195-memory-port.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/clock/mt8195-clk.h>

    #include <dt-bindings/power/mt8195-power.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        jpgdec-master {

            compatible = "mediatek,mt8195-jpgdec";

            power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;

            iommus = <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA0>,

                     <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA0>,

                     <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA1>,

                     <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA1>,

                     <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,

                     <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;

            dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;

            #address-cells = <2>;

            #size-cells = <2>;

            ranges;



            jpgdec@1a040000 {

                compatible = "mediatek,mt8195-jpgdec-hw";

                reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */

                iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,

                         <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,

                         <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,

                         <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,

                         <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,

                         <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;

                interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;

                clocks = <&vencsys CLK_VENC_JPGDEC>;

                clock-names = "jpgdec";

                power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;

            };



            jpgdec@1a050000 {

                compatible = "mediatek,mt8195-jpgdec-hw";

                reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */

                iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,

                         <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,

                         <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,

                         <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,

                         <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,

                         <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;

                interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;

                clocks = <&vencsys CLK_VENC_JPGDEC_C1>;

                clock-names = "jpgdec";

                power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;

            };



            jpgdec@1b040000 {

                compatible = "mediatek,mt8195-jpgdec-hw";

                reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */

                iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,

                         <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,

                         <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,

                         <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,

                         <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,

                         <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;

                interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;

                clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;

                clock-names = "jpgdec";

                power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;

            };

        };

    };

Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegenc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek JPEG Encoder



maintainers:

  - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com>



description:

  MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs



properties:

  compatible:

    const: mediatek,mt8195-jpgenc



  power-domains:

    maxItems: 1



  iommus:

    maxItems: 4

    description:

      Points to the respective IOMMU block with master port as argument, see

      Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.

      Ports are according to the HW.



  dma-ranges:

    maxItems: 1

    description: |

      Describes the physical address space of IOMMU maps to memory.



  "#address-cells":

    const: 2



  "#size-cells":

    const: 2



  ranges: true



# Required child node:

patternProperties:

  "^jpgenc@[0-9a-f]+$":

    type: object

    description:

      The jpeg encoder hardware device node which should be added as subnodes to

      the main jpeg node.



    properties:

      compatible:

        const: mediatek,mt8195-jpgenc-hw



      reg:

        maxItems: 1



      iommus:

        minItems: 1

        maxItems: 32

        description:

          List of the hardware port in respective IOMMU block for current Socs.

          Refer to bindings/iommu/mediatek,iommu.yaml.



      interrupts:

        maxItems: 1



      clocks:

        maxItems: 1



      clock-names:

        items:

          - const: jpgenc



      power-domains:

        maxItems: 1



    required:

      - compatible

      - reg

      - iommus

      - interrupts

      - clocks

      - clock-names

      - power-domains



    additionalProperties: false



required:

  - compatible

  - power-domains

  - iommus

  - dma-ranges

  - ranges



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/memory/mt8195-memory-port.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/clock/mt8195-clk.h>

    #include <dt-bindings/power/mt8195-power.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        jpgenc-master {

            compatible = "mediatek,mt8195-jpgenc";

            power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;

            iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,

                     <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,

                     <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,

                     <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;

            dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;

            #address-cells = <2>;

            #size-cells = <2>;

            ranges;



            jpgenc@1a030000 {

                compatible = "mediatek,mt8195-jpgenc-hw";

                reg = <0 0x1a030000 0 0x10000>;

                iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>,

                         <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>,

                         <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>,

                         <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>;

                interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>;

                clocks = <&vencsys CLK_VENC_JPGENC>;

                clock-names = "jpgenc";

                power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;

            };



            jpgenc@1b030000 {

                compatible = "mediatek,mt8195-jpgenc-hw";

                reg = <0 0x1b030000 0 0x10000>;

                iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,

                         <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,

                         <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,

                         <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;

                interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>;

                clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>;

                clock-names = "jpgenc";

                power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;

            };

        };

    };

Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml

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@@ -22,6 +22,7 @@ properties: 
      - items:

          - enum:

              - mediatek,mt7623-jpgdec

              - mediatek,mt8188-jpgdec

          - const: mediatek,mt2701-jpgdec



  reg:

Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml

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@@ -19,6 +19,7 @@ properties: 
          - mediatek,mt2701-jpgenc

          - mediatek,mt8183-jpgenc

          - mediatek,mt8186-jpgenc

          - mediatek,mt8188-jpgenc

      - const: mediatek,mtk-jpgenc

  reg:

    maxItems: 1

drivers/media/platform/mediatek/jpeg/Makefile

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# SPDX-License-Identifier: GPL-2.0-only

mtk_jpeg-objs := mtk_jpeg_core.o \

		 mtk_jpeg_dec_hw.o \

		 mtk_jpeg_dec_parse.o \

		 mtk_jpeg_enc_hw.o

obj-$(CONFIG_VIDEO_MEDIATEK_JPEG) += mtk_jpeg.o
 
obj-$(CONFIG_VIDEO_MEDIATEK_JPEG) += mtk_jpeg.o \

	mtk-jpeg-enc-hw.o \

	mtk-jpeg-dec-hw.o



mtk_jpeg-y := mtk_jpeg_core.o \

		 mtk_jpeg_dec_parse.o



mtk-jpeg-enc-hw-y := mtk_jpeg_enc_hw.o

mtk-jpeg-dec-hw-y := mtk_jpeg_dec_hw.o