Commit dd4f373e authored by Roy-CW.Yeh's avatar Roy-CW.Yeh Committed by Matthias Brugger
Browse files

soc: mediatek: mmsys: add config api for RSZ switching and DCM 



Due to MT8195 HW design, some RSZs have additional settings that
need to be configured in MMSYS.

Signed-off-by: default avatarRoy-CW.Yeh <roy-cw.yeh@mediatek.com>
Signed-off-by: default avatarMoudy Ho <moudy.ho@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Change-Id: I41978bf14951221c88abbe70d8c24cb0770e11e3
Link: https://lore.kernel.org/r/20230206091109.1324-5-moudy.ho@mediatek.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 7ceff25a

drivers/soc/mediatek/mt8195-mmsys.h

+13 −0
Original line number Diff line number Diff line
@@ -146,6 +146,19 @@ 
#define MT8195_VDO1_MIXER_SOUT_SEL_IN				0xf68

#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER			0



/* VPPSYS1 */

#define MT8195_VPP1_HW_DCM_1ST_DIS0				0x150

#define MT8195_VPP1_HW_DCM_1ST_DIS1				0x160

#define MT8195_VPP1_HW_DCM_2ND_DIS0				0x1a0

#define MT8195_VPP1_HW_DCM_2ND_DIS1				0x1b0

#define MT8195_SVPP2_BUF_BF_RSZ_SWITCH				0xf48

#define MT8195_SVPP3_BUF_BF_RSZ_SWITCH				0xf74



/* VPPSYS1 HW DCM client*/

#define MT8195_SVPP1_MDP_RSZ					BIT(25)

#define MT8195_SVPP2_MDP_RSZ					BIT(4)

#define MT8195_SVPP3_MDP_RSZ					BIT(5)



static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {

	{

		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,

drivers/soc/mediatek/mtk-mmsys.c

+44 −0
Original line number Diff line number Diff line
@@ -242,6 +242,50 @@ void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val) 
}

EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_dpi_fmt_config);



void mtk_mmsys_vpp_rsz_merge_config(struct device *dev, u32 id, bool enable,

				    struct cmdq_pkt *cmdq_pkt)

{

	u32 reg;



	switch (id) {

	case 2:

		reg = MT8195_SVPP2_BUF_BF_RSZ_SWITCH;

		break;

	case 3:

		reg = MT8195_SVPP3_BUF_BF_RSZ_SWITCH;

		break;

	default:

		dev_err(dev, "Invalid id %d\n", id);

		return;

	}



	mtk_mmsys_update_bits(dev_get_drvdata(dev), reg, ~0, enable, cmdq_pkt);

}

EXPORT_SYMBOL_GPL(mtk_mmsys_vpp_rsz_merge_config);



void mtk_mmsys_vpp_rsz_dcm_config(struct device *dev, bool enable,

				  struct cmdq_pkt *cmdq_pkt)

{

	u32 client;



	client = MT8195_SVPP1_MDP_RSZ;

	mtk_mmsys_update_bits(dev_get_drvdata(dev),

			      MT8195_VPP1_HW_DCM_1ST_DIS0, client,

			      ((enable) ? client : 0), cmdq_pkt);

	mtk_mmsys_update_bits(dev_get_drvdata(dev),

			      MT8195_VPP1_HW_DCM_2ND_DIS0, client,

			      ((enable) ? client : 0), cmdq_pkt);



	client = MT8195_SVPP2_MDP_RSZ | MT8195_SVPP3_MDP_RSZ;

	mtk_mmsys_update_bits(dev_get_drvdata(dev),

			      MT8195_VPP1_HW_DCM_1ST_DIS1, client,

			      ((enable) ? client : 0), cmdq_pkt);

	mtk_mmsys_update_bits(dev_get_drvdata(dev),

			      MT8195_VPP1_HW_DCM_2ND_DIS1, client,

			      ((enable) ? client : 0), cmdq_pkt);

}

EXPORT_SYMBOL_GPL(mtk_mmsys_vpp_rsz_dcm_config);



static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,

				  bool assert)

{

include/linux/soc/mediatek/mtk-mmsys.h

+6 −0
Original line number Diff line number Diff line
@@ -99,4 +99,10 @@ void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 
void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap,

				     struct cmdq_pkt *cmdq_pkt);



void mtk_mmsys_vpp_rsz_merge_config(struct device *dev, u32 id, bool enable,

				    struct cmdq_pkt *cmdq_pkt);



void mtk_mmsys_vpp_rsz_dcm_config(struct device *dev, bool enable,

				  struct cmdq_pkt *cmdq_pkt);



#endif /* __MTK_MMSYS_H */