Commit de4f30fd authored by Peter De Schrijver's avatar Peter De Schrijver
Browse files

clk: tegra: move PMC, fixed clocks to common files 



Introduce new files for fixed and PMC clocks common between several Tegra
SoCs and move Tegra114 to this new infrastructure.

Signed-off-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
parent 76ebc134

drivers/clk/tegra/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -8,6 +8,8 @@ obj-y += clk-pll-out.o 
obj-y					+= clk-super.o

obj-y					+= clk-tegra-audio.o

obj-y					+= clk-tegra-periph.o

obj-y					+= clk-tegra-pmc.o

obj-y					+= clk-tegra-fixed.o

obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clk-tegra20.o

obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += clk-tegra30.o

obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= clk-tegra114.o

drivers/clk/tegra/clk-tegra-fixed.c

0 → 100644
+111 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */



#include <linux/io.h>

#include <linux/clk.h>

#include <linux/clk-provider.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/delay.h>

#include <linux/export.h>

#include <linux/clk/tegra.h>



#include "clk.h"

#include "clk-id.h"



#define OSC_CTRL			0x50

#define OSC_CTRL_OSC_FREQ_SHIFT		28

#define OSC_CTRL_PLL_REF_DIV_SHIFT	26



int __init tegra_osc_clk_init(void __iomem *clk_base,

				struct tegra_clk *tegra_clks,

				unsigned long *input_freqs, int num,

				unsigned long *osc_freq,

				unsigned long *pll_ref_freq)

{

	struct clk *clk;

	struct clk **dt_clk;

	u32 val, pll_ref_div;

	unsigned osc_idx;



	val = readl_relaxed(clk_base + OSC_CTRL);

	osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;



	if (osc_idx < num)

		*osc_freq = input_freqs[osc_idx];

	else

		*osc_freq = 0;



	if (!*osc_freq) {

		WARN_ON(1);

		return -EINVAL;

	}



	dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, tegra_clks);

	if (!dt_clk)

		return 0;



	clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,

				      *osc_freq);

	*dt_clk = clk;



	/* pll_ref */

	val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;

	pll_ref_div = 1 << val;

	dt_clk = tegra_lookup_dt_id(tegra_clk_pll_ref, tegra_clks);

	if (!dt_clk)

		return 0;



	clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",

					0, 1, pll_ref_div);

	*dt_clk = clk;



	if (pll_ref_freq)

		*pll_ref_freq = *osc_freq / pll_ref_div;



	return 0;

}



void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)

{

	struct clk *clk;

	struct clk **dt_clk;



	/* clk_32k */

	dt_clk = tegra_lookup_dt_id(tegra_clk_clk_32k, tegra_clks);

	if (dt_clk) {

		clk = clk_register_fixed_rate(NULL, "clk_32k", NULL,

					CLK_IS_ROOT, 32768);

		*dt_clk = clk;

	}



	/* clk_m_div2 */

	dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div2, tegra_clks);

	if (dt_clk) {

		clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",

					CLK_SET_RATE_PARENT, 1, 2);

		*dt_clk = clk;

	}



	/* clk_m_div4 */

	dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div4, tegra_clks);

	if (dt_clk) {

		clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",

					CLK_SET_RATE_PARENT, 1, 4);

		*dt_clk = clk;

	}

}

drivers/clk/tegra/clk-tegra-pmc.c

0 → 100644
+132 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */



#include <linux/io.h>

#include <linux/clk.h>

#include <linux/clk-provider.h>

#include <linux/clkdev.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/delay.h>

#include <linux/export.h>

#include <linux/clk/tegra.h>



#include "clk.h"

#include "clk-id.h"



#define PMC_CLK_OUT_CNTRL 0x1a8

#define PMC_DPD_PADS_ORIDE 0x1c

#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20

#define PMC_CTRL 0

#define PMC_CTRL_BLINK_ENB 7

#define PMC_BLINK_TIMER 0x40



struct pmc_clk_init_data {

	char *mux_name;

	char *gate_name;

	const char **parents;

	int num_parents;

	int mux_id;

	int gate_id;

	char *dev_name;

	u8 mux_shift;

	u8 gate_shift;

};



#define PMC_CLK(_num, _mux_shift, _gate_shift)\

	{\

		.mux_name = "clk_out_" #_num "_mux",\

		.gate_name = "clk_out_" #_num,\

		.parents = clk_out ##_num ##_parents,\

		.num_parents = ARRAY_SIZE(clk_out ##_num ##_parents),\

		.mux_id = tegra_clk_clk_out_ ##_num ##_mux,\

		.gate_id = tegra_clk_clk_out_ ##_num,\

		.dev_name = "extern" #_num,\

		.mux_shift = _mux_shift,\

		.gate_shift = _gate_shift,\

	}



static DEFINE_SPINLOCK(clk_out_lock);



static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",

	"clk_m_div4", "extern1",

};



static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",

	"clk_m_div4", "extern2",

};



static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",

	"clk_m_div4", "extern3",

};



static struct pmc_clk_init_data pmc_clks[] = {

	PMC_CLK(1, 6, 2),

	PMC_CLK(2, 14, 10),

	PMC_CLK(3, 22, 18),

};



void __init tegra_pmc_clk_init(void __iomem *pmc_base,

				struct tegra_clk *tegra_clks)

{

	struct clk *clk;

	struct clk **dt_clk;

	int i;



	for (i = 0; i < ARRAY_SIZE(pmc_clks); i++) {

		struct pmc_clk_init_data *data;



		data = pmc_clks + i;



		dt_clk = tegra_lookup_dt_id(data->mux_id, tegra_clks);

		if (!dt_clk)

			continue;



		clk = clk_register_mux(NULL, data->mux_name, data->parents,

				data->num_parents, CLK_SET_RATE_NO_REPARENT,

				pmc_base + PMC_CLK_OUT_CNTRL, data->mux_shift,

				3, 0, &clk_out_lock);

		*dt_clk = clk;





		dt_clk = tegra_lookup_dt_id(data->gate_id, tegra_clks);

		if (!dt_clk)

			continue;



		clk = clk_register_gate(NULL, data->gate_name, data->mux_name,

					0, pmc_base + PMC_CLK_OUT_CNTRL,

					data->gate_shift, 0, &clk_out_lock);

		*dt_clk = clk;

		clk_register_clkdev(clk, data->dev_name, data->gate_name);

	}



	/* blink */

	writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);

	clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,

				pmc_base + PMC_DPD_PADS_ORIDE,

				PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);



	dt_clk = tegra_lookup_dt_id(tegra_clk_blink, tegra_clks);

	if (!dt_clk)

		return;



	clk = clk_register_gate(NULL, "blink", "blink_override", 0,

				pmc_base + PMC_CTRL,

				PMC_CTRL_BLINK_ENB, 0, NULL);

	clk_register_clkdev(clk, "blink", NULL);

	*dt_clk = clk;

}

drivers/clk/tegra/clk-tegra114.c

+1 −74
Original line number Diff line number Diff line
@@ -107,13 +107,6 @@ 
#define PLLC_OUT 0x84

#define PLLM_OUT 0x94



#define PMC_CLK_OUT_CNTRL 0x1a8

#define PMC_DPD_PADS_ORIDE 0x1c

#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20

#define PMC_CTRL 0

#define PMC_CTRL_BLINK_ENB 7

#define PMC_BLINK_TIMER 0x40



#define OSC_CTRL			0x50

#define OSC_CTRL_OSC_FREQ_SHIFT		28

#define OSC_CTRL_PLL_REF_DIV_SHIFT	26
@@ -177,7 +170,6 @@ static DEFINE_SPINLOCK(pll_d_lock); 
static DEFINE_SPINLOCK(pll_d2_lock);

static DEFINE_SPINLOCK(pll_u_lock);

static DEFINE_SPINLOCK(pll_re_lock);

static DEFINE_SPINLOCK(clk_out_lock);

static DEFINE_SPINLOCK(sysrate_lock);



static struct div_nmp pllxc_nmp = {
@@ -1199,71 +1191,6 @@ static void __init tegra114_pll_init(void __iomem *clk_base, 
	clks[TEGRA114_CLK_PLL_E_OUT0] = clk;

}



static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",

	"clk_m_div4", "extern1",

};



static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",

	"clk_m_div4", "extern2",

};



static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",

	"clk_m_div4", "extern3",

};



static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)

{

	struct clk *clk;



	/* clk_out_1 */

	clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,

			       ARRAY_SIZE(clk_out1_parents),

			       CLK_SET_RATE_NO_REPARENT,

			       pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,

			       &clk_out_lock);

	clks[TEGRA114_CLK_CLK_OUT_1_MUX] = clk;

	clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0,

				pmc_base + PMC_CLK_OUT_CNTRL, 2, 0,

				&clk_out_lock);

	clks[TEGRA114_CLK_CLK_OUT_1] = clk;



	/* clk_out_2 */

	clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,

			       ARRAY_SIZE(clk_out2_parents),

			       CLK_SET_RATE_NO_REPARENT,

			       pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,

			       &clk_out_lock);

	clks[TEGRA114_CLK_CLK_OUT_2_MUX] = clk;

	clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,

				pmc_base + PMC_CLK_OUT_CNTRL, 10, 0,

				&clk_out_lock);

	clks[TEGRA114_CLK_CLK_OUT_2] = clk;



	/* clk_out_3 */

	clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,

			       ARRAY_SIZE(clk_out3_parents),

			       CLK_SET_RATE_NO_REPARENT,

			       pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,

			       &clk_out_lock);

	clks[TEGRA114_CLK_CLK_OUT_3_MUX] = clk;

	clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,

				pmc_base + PMC_CLK_OUT_CNTRL, 18, 0,

				&clk_out_lock);

	clks[TEGRA114_CLK_CLK_OUT_3] = clk;



	/* blink */

	/* clear the blink timer register to directly output clk_32k */

	writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);

	clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,

				pmc_base + PMC_DPD_PADS_ORIDE,

				PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);

	clk = clk_register_gate(NULL, "blink", "blink_override", 0,

				pmc_base + PMC_CTRL,

				PMC_CTRL_BLINK_ENB, 0, NULL);

	clks[TEGRA114_CLK_BLINK] = clk;



}



static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",

			       "pll_p", "pll_p_out2", "unused",

			       "clk_32k", "pll_m_out1" };
@@ -1612,7 +1539,7 @@ static void __init tegra114_clock_init(struct device_node *np) 
	tegra114_pll_init(clk_base, pmc_base);

	tegra114_periph_clk_init(clk_base, pmc_base);

	tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks, &pll_a_params);

	tegra114_pmc_clk_init(pmc_base);

	tegra_pmc_clk_init(pmc_base, tegra114_clks);

	tegra114_super_clk_init(clk_base);



	tegra_add_of_provider(np);

drivers/clk/tegra/clk.h

+7 −0
Original line number Diff line number Diff line
@@ -604,6 +604,13 @@ void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base, 
			struct tegra_clk *tegra_clks,

			struct tegra_clk_pll_params *pll_params);



void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks);

void tegra_fixed_clk_init(struct tegra_clk *tegra_clks);

int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks,

				unsigned long *input_freqs, int num,

				unsigned long *osc_freq,

				unsigned long *pll_ref_freq);



void tegra114_clock_tune_cpu_trimmers_high(void);

void tegra114_clock_tune_cpu_trimmers_low(void);

void tegra114_clock_tune_cpu_trimmers_init(void);