Commit de60edf1 authored by Nishanth Menon's avatar Nishanth Menon
Browse files

arm64: dts: ti: k3-am64: Fix gic-v3 compatible regs 

Though GIC ARE option is disabled for no GIC-v2 compatibility,
Cortex-A53 is free to implement the CPU interface as long as it
communicates with the GIC using the stream protocol. This requires
that the SoC integration mark out the PERIPHBASE[1] as reserved area
within the SoC. See longer discussion in [2] for further information.

Update the GIC register map to indicate offsets from PERIPHBASE based
on [3]. Without doing this, systems like kvm will not function with
gic-v2 emulation.

[1] https://developer.arm.com/documentation/ddi0500/e/system-control/aarch64-register-descriptions/configuration-base-address-register--el1
[2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/
[3] https://developer.arm.com/documentation/ddi0500/e/generic-interrupt-controller-cpu-interface/gic-programmers-model/memory-map



Cc: stable@vger.kernel.org
Fixes: 8abae938 ("arm64: dts: ti: Add support for AM642 SoC")
Reported-by: default avatarMarc Zyngier <maz@kernel.org>
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Acked-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220215201008.15235-5-nm@ti.com
parent 1a307cc2

arch/arm64/boot/dts/ti/k3-am64-main.dtsi

+4 −1
Original line number Diff line number Diff line
@@ -59,7 +59,10 @@ gic500: interrupt-controller@1800000 { 
		#interrupt-cells = <3>;

		interrupt-controller;

		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */

		      <0x00 0x01840000 0x00 0xC0000>;	/* GICR */

		      <0x00 0x01840000 0x00 0xC0000>,	/* GICR */

		      <0x01 0x00000000 0x00 0x2000>,	/* GICC */

		      <0x01 0x00010000 0x00 0x1000>,	/* GICH */

		      <0x01 0x00020000 0x00 0x2000>;	/* GICV */

		/*

		 * vcpumntirq:

		 * virtual CPU interface maintenance interrupt

arch/arm64/boot/dts/ti/k3-am64.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -90,6 +90,7 @@ cbass_main: bus@f4000 { 
			 <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */

			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */

			 <0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */

			 <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */

			 <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */

			 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */