Commit df43ce48 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-meson-v6.3-1' of https://github.com/BayLibre/clk-meson into clk-amlogic 

Pull Amlogic clk updates from Jerome Brunet:

 - Use .determine_rate() instead of .round_rate() for the dualdiv, mpll,
   sclk-div and cpu-dyn-div amlogic clock drivers

* tag 'clk-meson-v6.3-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rate
  clk: meson: sclk-div: switch from .round_rate to .determine_rate
  clk: meson: dualdiv: switch from .round_rate to .determine_rate
  clk: meson: mpll: Switch from .round_rate to .determine_rate
parents 1b929c02 716592fd

drivers/clk/meson/clk-cpu-dyndiv.c

+4 −5
Original line number Original line Diff line number Diff line
@@ -27,14 +27,13 @@ static unsigned long meson_clk_cpu_dyndiv_recalc_rate(struct clk_hw *hw, 
				   NULL, 0, data->div.width);

				   NULL, 0, data->div.width);

}

}





static long meson_clk_cpu_dyndiv_round_rate(struct clk_hw *hw,

static int meson_clk_cpu_dyndiv_determine_rate(struct clk_hw *hw,

					    unsigned long rate,

					       struct clk_rate_request *req)

					    unsigned long *prate)

{

{

	struct clk_regmap *clk = to_clk_regmap(hw);

	struct clk_regmap *clk = to_clk_regmap(hw);

	struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);

	struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);





	return divider_round_rate(hw, rate, prate, NULL, data->div.width, 0);

	return divider_determine_rate(hw, req, NULL, data->div.width, 0);

}

}





static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate,

static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -63,7 +62,7 @@ static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate, 




const struct clk_ops meson_clk_cpu_dyndiv_ops = {

const struct clk_ops meson_clk_cpu_dyndiv_ops = {

	.recalc_rate = meson_clk_cpu_dyndiv_recalc_rate,

	.recalc_rate = meson_clk_cpu_dyndiv_recalc_rate,

	.round_rate = meson_clk_cpu_dyndiv_round_rate,

	.determine_rate = meson_clk_cpu_dyndiv_determine_rate,

	.set_rate = meson_clk_cpu_dyndiv_set_rate,

	.set_rate = meson_clk_cpu_dyndiv_set_rate,

};

};

EXPORT_SYMBOL_GPL(meson_clk_cpu_dyndiv_ops);

EXPORT_SYMBOL_GPL(meson_clk_cpu_dyndiv_ops);

drivers/clk/meson/clk-dualdiv.c

+13 −8
Original line number Original line Diff line number Diff line
@@ -86,18 +86,23 @@ __dualdiv_get_setting(unsigned long rate, unsigned long parent_rate, 
	return (struct meson_clk_dualdiv_param *)&table[best_i];

	return (struct meson_clk_dualdiv_param *)&table[best_i];

}

}





static long meson_clk_dualdiv_round_rate(struct clk_hw *hw, unsigned long rate,

static int meson_clk_dualdiv_determine_rate(struct clk_hw *hw,

					 unsigned long *parent_rate)

					    struct clk_rate_request *req)

{

{

	struct clk_regmap *clk = to_clk_regmap(hw);

	struct clk_regmap *clk = to_clk_regmap(hw);

	struct meson_clk_dualdiv_data *dualdiv = meson_clk_dualdiv_data(clk);

	struct meson_clk_dualdiv_data *dualdiv = meson_clk_dualdiv_data(clk);

	const struct meson_clk_dualdiv_param *setting =

	const struct meson_clk_dualdiv_param *setting;

		__dualdiv_get_setting(rate, *parent_rate, dualdiv);





	if (!setting)

	setting = __dualdiv_get_setting(req->rate, req->best_parent_rate,

		return meson_clk_dualdiv_recalc_rate(hw, *parent_rate);

					dualdiv);

	if (setting)

		req->rate = __dualdiv_param_to_rate(req->best_parent_rate,

						    setting);

	else

		req->rate = meson_clk_dualdiv_recalc_rate(hw,

							  req->best_parent_rate);





	return __dualdiv_param_to_rate(*parent_rate, setting);

	return 0;

}

}





static int meson_clk_dualdiv_set_rate(struct clk_hw *hw, unsigned long rate,

static int meson_clk_dualdiv_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -122,7 +127,7 @@ static int meson_clk_dualdiv_set_rate(struct clk_hw *hw, unsigned long rate, 




const struct clk_ops meson_clk_dualdiv_ops = {

const struct clk_ops meson_clk_dualdiv_ops = {

	.recalc_rate	= meson_clk_dualdiv_recalc_rate,

	.recalc_rate	= meson_clk_dualdiv_recalc_rate,

	.round_rate	= meson_clk_dualdiv_round_rate,

	.determine_rate	= meson_clk_dualdiv_determine_rate,

	.set_rate	= meson_clk_dualdiv_set_rate,

	.set_rate	= meson_clk_dualdiv_set_rate,

};

};

EXPORT_SYMBOL_GPL(meson_clk_dualdiv_ops);

EXPORT_SYMBOL_GPL(meson_clk_dualdiv_ops);

drivers/clk/meson/clk-mpll.c

+13 −7
Original line number Original line Diff line number Diff line
@@ -87,16 +87,22 @@ static unsigned long mpll_recalc_rate(struct clk_hw *hw, 
	return rate < 0 ? 0 : rate;

	return rate < 0 ? 0 : rate;

}

}





static long mpll_round_rate(struct clk_hw *hw,

static int mpll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)

			    unsigned long rate,

			    unsigned long *parent_rate)

{

{

	struct clk_regmap *clk = to_clk_regmap(hw);

	struct clk_regmap *clk = to_clk_regmap(hw);

	struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);

	struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);

	unsigned int sdm, n2;

	unsigned int sdm, n2;

	long rate;



	params_from_rate(req->rate, req->best_parent_rate, &sdm, &n2,

			 mpll->flags);





	params_from_rate(rate, *parent_rate, &sdm, &n2, mpll->flags);

	rate = rate_from_params(req->best_parent_rate, sdm, n2);

	return rate_from_params(*parent_rate, sdm, n2);

	if (rate < 0)

		return rate;



	req->rate = rate;

	return 0;

}

}





static int mpll_set_rate(struct clk_hw *hw,

static int mpll_set_rate(struct clk_hw *hw,
@@ -157,13 +163,13 @@ static int mpll_init(struct clk_hw *hw) 




const struct clk_ops meson_clk_mpll_ro_ops = {

const struct clk_ops meson_clk_mpll_ro_ops = {

	.recalc_rate	= mpll_recalc_rate,

	.recalc_rate	= mpll_recalc_rate,

	.round_rate	= mpll_round_rate,

	.determine_rate	= mpll_determine_rate,

};

};

EXPORT_SYMBOL_GPL(meson_clk_mpll_ro_ops);

EXPORT_SYMBOL_GPL(meson_clk_mpll_ro_ops);





const struct clk_ops meson_clk_mpll_ops = {

const struct clk_ops meson_clk_mpll_ops = {

	.recalc_rate	= mpll_recalc_rate,

	.recalc_rate	= mpll_recalc_rate,

	.round_rate	= mpll_round_rate,

	.determine_rate	= mpll_determine_rate,

	.set_rate	= mpll_set_rate,

	.set_rate	= mpll_set_rate,

	.init		= mpll_init,

	.init		= mpll_init,

};

};

drivers/clk/meson/sclk-div.c

+6 −5
Original line number Original line Diff line number Diff line
@@ -96,16 +96,17 @@ static int sclk_div_bestdiv(struct clk_hw *hw, unsigned long rate, 
	return bestdiv;

	return bestdiv;

}

}





static long sclk_div_round_rate(struct clk_hw *hw, unsigned long rate,

static int sclk_div_determine_rate(struct clk_hw *hw,

				unsigned long *prate)

				   struct clk_rate_request *req)

{

{

	struct clk_regmap *clk = to_clk_regmap(hw);

	struct clk_regmap *clk = to_clk_regmap(hw);

	struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);

	struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);

	int div;

	int div;





	div = sclk_div_bestdiv(hw, rate, prate, sclk);

	div = sclk_div_bestdiv(hw, req->rate, &req->best_parent_rate, sclk);

	req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);





	return DIV_ROUND_UP_ULL((u64)*prate, div);

	return 0;

}

}





static void sclk_apply_ratio(struct clk_regmap *clk,

static void sclk_apply_ratio(struct clk_regmap *clk,
@@ -237,7 +238,7 @@ static int sclk_div_init(struct clk_hw *hw) 




const struct clk_ops meson_sclk_div_ops = {

const struct clk_ops meson_sclk_div_ops = {

	.recalc_rate	= sclk_div_recalc_rate,

	.recalc_rate	= sclk_div_recalc_rate,

	.round_rate	= sclk_div_round_rate,

	.determine_rate	= sclk_div_determine_rate,

	.set_rate	= sclk_div_set_rate,

	.set_rate	= sclk_div_set_rate,

	.enable		= sclk_div_enable,

	.enable		= sclk_div_enable,

	.disable	= sclk_div_disable,

	.disable	= sclk_div_disable,