Commit dfd10e7a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC platform changes from Olof Johansson:
 "New core SoC-specific changes.

  New platforms:
   * Introduction of a vendor, Hisilicon, and one of their SoCs with
     some random numerical product name.
   * Introduction of EFM32, embedded platform from Silicon Labs (ARMv7m,
     i.e. !MMU).
   * Marvell Berlin series of SoCs, which include the one in Chromecast.
   * MOXA platform support, ARM9-based platform used mostly in
     industrial products
   * Support for Freescale's i.MX50 SoC.

  Other work:
   * Renesas work for new platforms and drivers, and conversion over to
     more multiplatform-friendly device registration schemes.
   * SMP support for Allwinner sunxi platforms.
   * ... plus a bunch of other stuff across various platforms"

* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (201 commits)
  ARM: tegra: fix tegra_powergate_sequence_power_up() inline
  ARM: msm_defconfig: Update for multi-platform
  ARM: msm: Move MSM's DT based hardware to multi-platform support
  ARM: msm: Only build timer.c if required
  ARM: msm: Only build clock.c on proc_comm based platforms
  ARM: ux500: Enable system suspend with WFI support
  ARM: ux500: turn on PRINTK_TIME in u8500_defconfig
  ARM: shmobile: r8a7790: Fix I2C controller names
  ARM: msm: Simplify ARCH_MSM_DT config
  ARM: msm: Add support for MSM8974 SoC
  ARM: sunxi: select ARM_PSCI
  MAINTAINERS: Update Allwinner sunXi maintainer files
  ARM: sunxi: Select RESET_CONTROLLER
  ARM: imx: improve the comment of CCM lpm SW workaround
  ARM: imx: improve status check of clock gate
  ARM: imx: add necessary interface for pfd
  ARM: imx_v6_v7_defconfig: Select CONFIG_REGULATOR_PFUZE100
  ARM: imx_v6_v7_defconfig: Select MX35 and MX50 device tree support
  ARM: imx: Add cpu frequency scaling support
  ARM i.MX35: Add devicetree support.
  ...
parents f2c73464 6373bb71

Documentation/arm/Marvell/README

+24 −0
Original line number Original line Diff line number Diff line
@@ -211,6 +211,30 @@ MMP/MMP2 family (communication processor) 
   Linux kernel mach directory: arch/arm/mach-mmp

   Linux kernel mach directory: arch/arm/mach-mmp

   Linux kernel plat directory: arch/arm/plat-pxa

   Linux kernel plat directory: arch/arm/plat-pxa





Berlin family (Digital Entertainment)

-------------------------------------



  Flavors:

	88DE3005, Armada 1500-mini

		Design name:	BG2CD

		Core:		ARM Cortex-A9, PL310 L2CC

		Homepage:	http://www.marvell.com/digital-entertainment/armada-1500-mini/

	88DE3100, Armada 1500

		Design name:	BG2

		Core:		Marvell PJ4B (ARMv7), Tauros3 L2CC

		Homepage:	http://www.marvell.com/digital-entertainment/armada-1500/

		Product Brief:	http://www.marvell.com/digital-entertainment/armada-1500/assets/Marvell-ARMADA-1500-Product-Brief.pdf

	88DE????

		Design name:	BG3

		Core:		ARM Cortex-A15, CA15 integrated L2CC



  Homepage: http://www.marvell.com/digital-entertainment/

  Directory: arch/arm/mach-berlin



  Comments:

   * This line of SoCs is based on Marvell Sheeva or ARM Cortex CPUs

     with Synopsys DesignWare (IRQ, GPIO, Timers, ...) and PXA IP (SDHCI, USB, ETH, ...).



Long-term plans

Long-term plans

---------------

---------------

Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt

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+32 −0
Original line number Original line Diff line number Diff line 
Hisilicon Platforms Device Tree Bindings

----------------------------------------------------



Hi4511 Board

Required root node properties:

	- compatible = "hisilicon,hi3620-hi4511";



Hisilicon system controller



Required properties:

- compatible : "hisilicon,sysctrl"

- reg : Register address and size



Optional properties:

- smp-offset : offset in sysctrl for notifying slave cpu booting

		cpu 1, reg;

		cpu 2, reg + 0x4;

		cpu 3, reg + 0x8;

		If reg value is not zero, cpun exit wfi and go

- resume-offset : offset in sysctrl for notifying cpu0 when resume

- reboot-offset : offset in sysctrl for system reboot



Example:



	/* for Hi3620 */

	sysctrl: system-controller@fc802000 {

		compatible = "hisilicon,sysctrl";

		reg = <0xfc802000 0x1000>;

		smp-offset = <0x31c>;

		resume-offset = <0x308>;

		reboot-offset = <0x4>;

	};

Documentation/devicetree/bindings/arm/marvell,berlin.txt

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+24 −0
Original line number Original line Diff line number Diff line 
Marvell Berlin SoC Family Device Tree Bindings

---------------------------------------------------------------



Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500

shall have the following properties:



* Required root node properties:

compatible: must contain "marvell,berlin"



In addition, the above compatible shall be extended with the specific

SoC and board used. Currently known SoC compatibles are:

    "marvell,berlin2"      for Marvell Armada 1500 (BG2, 88DE3100),

    "marvell,berlin2cd"    for Marvell Armada 1500-mini (BG2CD, 88DE3005)

    "marvell,berlin2ct"    for Marvell Armada ? (BG2CT, 88DE????)

    "marvell,berlin3"      for Marvell Armada ? (BG3, 88DE????)



* Example:



/ {

	model = "Sony NSZ-GS7";

	compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";



	...

}

Documentation/devicetree/bindings/clock/imx35-clock.txt

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+113 −0
Original line number Original line Diff line number Diff line 
* Clock bindings for Freescale i.MX35



Required properties:

- compatible: Should be "fsl,imx35-ccm"

- reg: Address and length of the register set

- interrupts: Should contain CCM interrupt

- #clock-cells: Should be <1>



The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell.  The following is a full list of i.MX35

clocks and IDs.



	Clock			ID

	---------------------------

	ckih			0

	mpll			1

	ppll			2

	mpll_075		3

	arm			4

	hsp			5

	hsp_div			6

	hsp_sel			7

	ahb			8

	ipg			9

	arm_per_div		10

	ahb_per_div		11

	ipg_per			12

	uart_sel		13

	uart_div		14

	esdhc_sel		15

	esdhc1_div		16

	esdhc2_div		17

	esdhc3_div		18

	spdif_sel		19

	spdif_div_pre		20

	spdif_div_post		21

	ssi_sel			22

	ssi1_div_pre		23

	ssi1_div_post		24

	ssi2_div_pre		25

	ssi2_div_post		26

	usb_sel			27

	usb_div			28

	nfc_div			29

	asrc_gate		30

	pata_gate		31

	audmux_gate		32

	can1_gate		33

	can2_gate		34

	cspi1_gate		35

	cspi2_gate		36

	ect_gate		37

	edio_gate		38

	emi_gate		39

	epit1_gate		40

	epit2_gate		41

	esai_gate		42

	esdhc1_gate		43

	esdhc2_gate		44

	esdhc3_gate		45

	fec_gate		46

	gpio1_gate		47

	gpio2_gate		48

	gpio3_gate		49

	gpt_gate		50

	i2c1_gate		51

	i2c2_gate		52

	i2c3_gate		53

	iomuxc_gate		54

	ipu_gate		55

	kpp_gate		56

	mlb_gate		57

	mshc_gate		58

	owire_gate		59

	pwm_gate		60

	rngc_gate		61

	rtc_gate		62

	rtic_gate		63

	scc_gate		64

	sdma_gate		65

	spba_gate		66

	spdif_gate		67

	ssi1_gate		68

	ssi2_gate		69

	uart1_gate		70

	uart2_gate		71

	uart3_gate		72

	usbotg_gate		73

	wdog_gate		74

	max_gate		75

	admux_gate		76

	csi_gate		77

	csi_div			78

	csi_sel			79

	iim_gate		80

	gpu2d_gate		81



Examples:



clks: ccm@53f80000 {

	compatible = "fsl,imx35-ccm";

	reg = <0x53f80000 0x4000>;

	interrupts = <31>;

	#clock-cells = <1>;

};



esdhc1: esdhc@53fb4000 {

	compatible = "fsl,imx35-esdhc";

	reg = <0x53fb4000 0x4000>;

	interrupts = <7>;

	clocks = <&clks 9>, <&clks 8>, <&clks 43>;

	clock-names = "ipg", "ahb", "per";

};

Documentation/devicetree/bindings/clock/imx5-clock.txt

+3 −192
Original line number Original line Diff line number Diff line
@@ -7,197 +7,8 @@ Required properties: 
- #clock-cells: Should be <1>

- #clock-cells: Should be <1>





The clock consumer should specify the desired clock by having the clock

The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell.  The following is a full list of i.MX5

ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx5-clock.h

clocks and IDs.

for the full list of i.MX5 clock IDs.



	Clock			ID

	---------------------------

	dummy			0

	ckil			1

	osc			2

	ckih1			3

	ckih2			4

	ahb			5

	ipg			6

	axi_a			7

	axi_b			8

	uart_pred		9

	uart_root		10

	esdhc_a_pred		11

	esdhc_b_pred		12

	esdhc_c_s		13

	esdhc_d_s		14

	emi_sel			15

	emi_slow_podf		16

	nfc_podf		17

	ecspi_pred		18

	ecspi_podf		19

	usboh3_pred		20

	usboh3_podf		21

	usb_phy_pred		22

	usb_phy_podf		23

	cpu_podf		24

	di_pred			25

	tve_s			27

	uart1_ipg_gate		28

	uart1_per_gate		29

	uart2_ipg_gate		30

	uart2_per_gate		31

	uart3_ipg_gate		32

	uart3_per_gate		33

	i2c1_gate		34

	i2c2_gate		35

	gpt_ipg_gate		36

	pwm1_ipg_gate		37

	pwm1_hf_gate		38

	pwm2_ipg_gate		39

	pwm2_hf_gate		40

	gpt_hf_gate		41

	fec_gate		42

	usboh3_per_gate		43

	esdhc1_ipg_gate		44

	esdhc2_ipg_gate		45

	esdhc3_ipg_gate		46

	esdhc4_ipg_gate		47

	ssi1_ipg_gate		48

	ssi2_ipg_gate		49

	ssi3_ipg_gate		50

	ecspi1_ipg_gate		51

	ecspi1_per_gate		52

	ecspi2_ipg_gate		53

	ecspi2_per_gate		54

	cspi_ipg_gate		55

	sdma_gate		56

	emi_slow_gate		57

	ipu_s			58

	ipu_gate		59

	nfc_gate		60

	ipu_di1_gate		61

	vpu_s			62

	vpu_gate		63

	vpu_reference_gate	64

	uart4_ipg_gate		65

	uart4_per_gate		66

	uart5_ipg_gate		67

	uart5_per_gate		68

	tve_gate		69

	tve_pred		70

	esdhc1_per_gate		71

	esdhc2_per_gate		72

	esdhc3_per_gate		73

	esdhc4_per_gate		74

	usb_phy_gate		75

	hsi2c_gate		76

	mipi_hsc1_gate		77

	mipi_hsc2_gate		78

	mipi_esc_gate		79

	mipi_hsp_gate		80

	ldb_di1_div_3_5		81

	ldb_di1_div		82

	ldb_di0_div_3_5		83

	ldb_di0_div		84

	ldb_di1_gate		85

	can2_serial_gate	86

	can2_ipg_gate		87

	i2c3_gate		88

	lp_apm			89

	periph_apm		90

	main_bus		91

	ahb_max			92

	aips_tz1		93

	aips_tz2		94

	tmax1			95

	tmax2			96

	tmax3			97

	spba			98

	uart_sel		99

	esdhc_a_sel		100

	esdhc_b_sel		101

	esdhc_a_podf		102

	esdhc_b_podf		103

	ecspi_sel		104

	usboh3_sel		105

	usb_phy_sel		106

	iim_gate		107

	usboh3_gate		108

	emi_fast_gate		109

	ipu_di0_gate		110

	gpc_dvfs		111

	pll1_sw			112

	pll2_sw			113

	pll3_sw			114

	ipu_di0_sel		115

	ipu_di1_sel		116

	tve_ext_sel		117

	mx51_mipi		118

	pll4_sw			119

	ldb_di1_sel		120

	di_pll4_podf		121

	ldb_di0_sel		122

	ldb_di0_gate		123

	usb_phy1_gate		124

	usb_phy2_gate		125

	per_lp_apm		126

	per_pred1		127

	per_pred2		128

	per_podf		129

	per_root		130

	ssi_apm			131

	ssi1_root_sel		132

	ssi2_root_sel		133

	ssi3_root_sel		134

	ssi_ext1_sel		135

	ssi_ext2_sel		136

	ssi_ext1_com_sel	137

	ssi_ext2_com_sel	138

	ssi1_root_pred		139

	ssi1_root_podf		140

	ssi2_root_pred		141

	ssi2_root_podf		142

	ssi_ext1_pred		143

	ssi_ext1_podf		144

	ssi_ext2_pred		145

	ssi_ext2_podf		146

	ssi1_root_gate		147

	ssi2_root_gate		148

	ssi3_root_gate		149

	ssi_ext1_gate		150

	ssi_ext2_gate		151

	epit1_ipg_gate		152

	epit1_hf_gate		153

	epit2_ipg_gate		154

	epit2_hf_gate		155

	can_sel			156

	can1_serial_gate	157

	can1_ipg_gate		158

	owire_gate		159

	gpu3d_s			160

	gpu2d_s			161

	gpu3d_gate		162

	gpu2d_gate		163

	garb_gate		164

	cko1_sel		165

	cko1_podf		166

	cko1			167

	cko2_sel		168

	cko2_podf		169

	cko2			170

	srtc_gate		171

	pata_gate		172

	sata_gate		173

	spdif_xtal_sel		174

	spdif0_sel		175

	spdif1_sel		176

	spdif0_pred		177

	spdif0_podf		178

	spdif1_pred		179

	spdif1_podf		180

	spdif0_com_sel		181

	spdif1_com_sel		182

	spdif0_gate		183

	spdif1_gate		184

	spdif_ipg_gate		185

	ocram			186





Examples (for mx53):

Examples (for mx53):
@@ -212,7 +23,7 @@ can1: can@53fc8000 { 
	compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";

	compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";

	reg = <0x53fc8000 0x4000>;

	reg = <0x53fc8000 0x4000>;

	interrupts = <82>;

	interrupts = <82>;

	clocks = <&clks 158>, <&clks 157>;

	clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>;

	clock-names = "ipg", "per";

	clock-names = "ipg", "per";

	status = "disabled";

	status = "disabled";

};
 
};