Commit e2c09648 authored by Peter De Schrijver's avatar Peter De Schrijver Committed by Thierry Reding
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dt-bindings: reserved-memory: Add support for DRAM MRQ GSCs 



Add bindings for DRAM MRQ GSC support.

Co-developed-by: default avatarStefan Kristiansson <stefank@nvidia.com>
Signed-off-by: default avatarStefan Kristiansson <stefank@nvidia.com>
Signed-off-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 22af900b

Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Tegra CPU-NS - BPMP IPC reserved memory



maintainers:

  - Peter De Schrijver <pdeschrijver@nvidia.com>



description: |

  Define a memory region used for communication between CPU-NS and BPMP.

  Typically this node is created by the bootloader as the physical address

  has to be known to both CPU-NS and BPMP for correct IPC operation.

  The memory region is defined using a child node under /reserved-memory.

  The sub-node is named shmem@<address>.



allOf:

  - $ref: reserved-memory.yaml



properties:

  compatible:

    const: nvidia,tegra264-bpmp-shmem



  reg:

    description: The physical address and size of the shared SDRAM region



unevaluatedProperties: false



required:

  - compatible

  - reg

  - no-map



examples:

  - |

    reserved-memory {

       #address-cells = <2>;

       #size-cells = <2>;

       dram_cpu_bpmp_mail: shmem@f1be0000 {

           compatible = "nvidia,tegra264-bpmp-shmem";

           reg = <0x0 0xf1be0000 0x0 0x2000>;

           no-map;

       };

    };

...