Commit e387d448 authored Oct 18, 2021 by Chanho Park Committed by Martin K. Petersen Oct 27, 2021

scsi: ufs: ufs-exynos: Change pclk available max value

To support 167MHz PCLK, we need to adjust the maximum value.

Link: https://lore.kernel.org/r/20211018124216.153072-4-chanho61.park@samsung.com


Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>

parent 10fb4f87

drivers/scsi/ufs/ufs-exynos.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -99,7 +99,7 @@ struct exynos_ufs;
		#define PA_HIBERN8TIME_VAL 0x20

		#define PCLK_AVAIL_MIN 70000000
		#define PCLK_AVAIL_MAX 133000000
		#define PCLK_AVAIL_MAX 167000000

		struct exynos_ufs_uic_attr {
		/* TX Attributes */