Commit e3969ead authored by Vinod Polimera's avatar Vinod Polimera Committed by Dmitry Baryshkov
Browse files

drm/msm/disp/dpu: get timing engine status from intf status register 



Recommended way of reading the interface timing gen status is via
status register. Timing gen status register will give a reliable status
of the interface especially during ON/OFF transitions. This support was
added from DPU version 5.0.0.

Signed-off-by: default avatarVinod Polimera <quic_vpolimer@quicinc.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/524724/
Link: https://lore.kernel.org/r/1677774797-31063-6-git-send-email-quic_vpolimer@quicinc.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent b6975693

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

+2 −1
Original line number Diff line number Diff line
@@ -78,7 +78,8 @@ 


#define INTF_SDM845_MASK (0)



#define INTF_SC7180_MASK BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE)

#define INTF_SC7180_MASK \

	(BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) | BIT(DPU_INTF_STATUS_SUPPORTED))



#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h

+7 −5
Original line number Diff line number Diff line
@@ -217,13 +217,15 @@ enum { 
 *                                  pixel data arrives to this INTF

 * @DPU_INTF_TE                     INTF block has TE configuration support

 * @DPU_DATA_HCTL_EN                Allows data to be transferred at different rate

                                than video timing

 *                                  than video timing

 * @DPU_INTF_STATUS_SUPPORTED       INTF block has INTF_STATUS register

 * @DPU_INTF_MAX

 */

enum {

	DPU_INTF_INPUT_CTRL = 0x1,

	DPU_INTF_TE,

	DPU_DATA_HCTL_EN,

	DPU_INTF_STATUS_SUPPORTED,

	DPU_INTF_MAX

};

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

+7 −1
Original line number Diff line number Diff line
@@ -62,6 +62,7 @@ 
#define   INTF_LINE_COUNT               0x0B0



#define   INTF_MUX                      0x25C

#define   INTF_STATUS                   0x26C



#define INTF_CFG_ACTIVE_H_EN	BIT(29)

#define INTF_CFG_ACTIVE_V_EN	BIT(30)
@@ -297,8 +298,13 @@ static void dpu_hw_intf_get_status( 
		struct intf_status *s)

{

	struct dpu_hw_blk_reg_map *c = &intf->hw;

	unsigned long cap = intf->cap->features;



	if (cap & BIT(DPU_INTF_STATUS_SUPPORTED))

		s->is_en = DPU_REG_READ(c, INTF_STATUS) & BIT(0);

	else

		s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN);



	s->is_prog_fetch_en = !!(DPU_REG_READ(c, INTF_CONFIG) & BIT(31));

	if (s->is_en) {

		s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT);