dt-bindings: display: samsung,exynos-fimd: convert to dtschema

Device-Tree bindings for Samsung SoC display controller (FIMD)

FIMD (Fully Interactive Mobile Display) is the Display Controller for the

Samsung series of SoCs which transfers the image data from a video memory

buffer to an external LCD interface.

Required properties:

- compatible: value should be one of the following

		"samsung,s3c2443-fimd"; /* for S3C24XX SoCs */

		"samsung,s3c6400-fimd"; /* for S3C64XX SoCs */

		"samsung,s5pv210-fimd"; /* for S5PV210 SoC */

		"samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */

		"samsung,exynos4210-fimd"; /* for Exynos4 SoCs */

		"samsung,exynos5250-fimd"; /* for Exynos5250 SoCs */

		"samsung,exynos5420-fimd"; /* for Exynos5420/5422/5800 SoCs */

- reg: physical base address and length of the FIMD registers set.

- interrupts: should contain a list of all FIMD IP block interrupts in the

		 order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier

		 format depends on the interrupt controller used.

- interrupt-names: should contain the interrupt names: "fifo", "vsync",

	"lcd_sys", in the same order as they were listed in the interrupts

        property.

- pinctrl-0: pin control group to be used for this controller.

- pinctrl-names: must contain a "default" entry.

- clocks: must include clock specifiers corresponding to entries in the

         clock-names property.

- clock-names: list of clock names sorted in the same order as the clocks

               property. Must contain "sclk_fimd" and "fimd".

Optional Properties:

- power-domains: a phandle to FIMD power domain node.

- samsung,invert-vden: video enable signal is inverted

- samsung,invert-vclk: video clock signal is inverted

- display-timings: timing settings for FIMD, as described in document [1].

		Can be used in case timings cannot be provided otherwise

		or to override timings provided by the panel.

- samsung,sysreg: handle to syscon used to control the system registers

- i80-if-timings: timing configuration for lcd i80 interface support.

  - cs-setup: clock cycles for the active period of address signal is enabled

              until chip select is enabled.

              If not specified, the default value(0) will be used.

  - wr-setup: clock cycles for the active period of CS signal is enabled until

              write signal is enabled.

              If not specified, the default value(0) will be used.

  - wr-active: clock cycles for the active period of CS is enabled.

               If not specified, the default value(1) will be used.

  - wr-hold: clock cycles for the active period of CS is disabled until write

             signal is disabled.

             If not specified, the default value(0) will be used.

  The parameters are defined as:

    VCLK(internal)  __|??????|_____|??????|_____|??????|_____|??????|_____|??

                      :            :            :            :            :

    Address Output  --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX

                      | cs-setup+1 |            :            :            :

                      |<---------->|            :            :            :

    Chip Select     ???????????????|____________:____________:____________|??

                                   | wr-setup+1 |            | wr-hold+1  |

                                   |<---------->|            |<---------->|

    Write Enable    ????????????????????????????|____________|???????????????

                                                | wr-active+1|

                                                |<---------->|

    Video Data      ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>--

The device node can contain 'port' child nodes according to the bindings defined

in [2]. The following are properties specific to those nodes:

- reg: (required) port index, can be:

		0 - for CAMIF0 input,

		1 - for CAMIF1 input,

		2 - for CAMIF2 input,

		3 - for parallel output,

		4 - for write-back interface

[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt

[2]: Documentation/devicetree/bindings/media/video-interfaces.txt

Example:

SoC specific DT entry:

	fimd@11c00000 {

		compatible = "samsung,exynos4210-fimd";

		interrupt-parent = <&combiner>;

		reg = <0x11c00000 0x20000>;

		interrupt-names = "fifo", "vsync", "lcd_sys";

		interrupts = <11 0>, <11 1>, <11 2>;

		clocks = <&clock 140>, <&clock 283>;

		clock-names = "sclk_fimd", "fimd";

		power-domains = <&pd_lcd0>;

		status = "disabled";

	};

Board specific DT entry:

	fimd@11c00000 {

		pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;

		pinctrl-names = "default";

		status = "okay";

	};

# SPDX-License-Identifier: GPL-2.0-only

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/samsung/samsung,fimd.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung S3C/S5P/Exynos SoC Fully Interactive Mobile Display (FIMD)

maintainers:

  - Inki Dae <inki.dae@samsung.com>

  - Joonyoung Shim <jy0922.shim@samsung.com>

  - Seung-Woo Kim <sw0312.kim@samsung.com>

  - Kyungmin Park <kyungmin.park@samsung.com>

  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>

properties:

  compatible:

    enum:

      - samsung,s3c2443-fimd

      - samsung,s3c6400-fimd

      - samsung,s5pv210-fimd

      - samsung,exynos3250-fimd

      - samsung,exynos4210-fimd

      - samsung,exynos5250-fimd

      - samsung,exynos5420-fimd

  '#address-cells':

    const: 1

  clocks:

    minItems: 2

    maxItems: 2

  clock-names:

    items:

      - const: sclk_fimd

      - const: fimd

  display-timings:

    $ref: ../panel/display-timings.yaml#

  i80-if-timings:

    type: object

    description: |

      Timing configuration for lcd i80 interface support.

      The parameters are defined as::

      VCLK(internal)  __|??????|_____|??????|_____|??????|_____|??????|_____|??

                        :            :            :            :            :

      Address Output  --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX

                        | cs-setup+1 |            :            :            :

                        |<---------->|            :            :            :

      Chip Select     ???????????????|____________:____________:____________|??

                                     | wr-setup+1 |            | wr-hold+1  |

                                     |<---------->|            |<---------->|

      Write Enable    ????????????????????????????|____________|???????????????

                                                  | wr-active+1|

                                                  |<---------->|

      Video Data      ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>--

    properties:

      cs-setup:

        $ref: /schemas/types.yaml#/definitions/uint32

        description:

          Clock cycles for the active period of address signal is enabled until

          chip select is enabled.

        default: 0

      wr-active:

        $ref: /schemas/types.yaml#/definitions/uint32

        description:

          Clock cycles for the active period of CS is enabled.

        default: 1

      wr-hold:

        $ref: /schemas/types.yaml#/definitions/uint32

        description:

          Clock cycles for the active period of CS is disabled until write

          signal is disabled.

        default: 0

      wr-setup:

        $ref: /schemas/types.yaml#/definitions/uint32

        description:

          Clock cycles for the active period of CS signal is enabled until

          write signal is enabled.

        default: 0

  iommus:

    minItems: 1

    maxItems: 2

  iommu-names:

    items:

      - const: m0

      - const: m1

  interrupts:

    items:

      - description: FIFO level

      - description: VSYNC

      - description: LCD system

  interrupt-names:

    items:

      - const: fifo

      - const: vsync

      - const: lcd_sys

  power-domains:

    maxItems: 1

  reg:

    maxItems: 1

  samsung,invert-vden:

    type: boolean

    description:

      Video enable signal is inverted.

  samsung,invert-vclk:

    type: boolean

    description:

      Video clock signal is inverted.

  samsung,sysreg:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      Phandle to System Register syscon.

  '#size-cells':

    const: 0

patternProperties:

  "^port@[0-4]+$":

    $ref: /schemas/graph.yaml#/properties/port

    description: |

      Contains ports with port with index::

       0 - for CAMIF0 input,

       1 - for CAMIF1 input,

       2 - for CAMIF2 input,

       3 - for parallel output,

       4 - for write-back interface

required:

  - compatible

  - clocks

  - clock-names

  - interrupts

  - interrupt-names

  - reg

allOf:

  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos5420-fimd

    then:

      properties:

        iommus:

          minItems: 2

          maxItems: 2

additionalProperties: false

examples:

  - |

    #include <dt-bindings/clock/exynos4.h>

    fimd@11c00000 {

        compatible = "samsung,exynos4210-fimd";

        interrupt-parent = <&combiner>;

        reg = <0x11c00000 0x20000>;

        interrupt-names = "fifo", "vsync", "lcd_sys";

        interrupts = <11 0>, <11 1>, <11 2>;

        clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;

        clock-names = "sclk_fimd", "fimd";

        power-domains = <&pd_lcd0>;

        iommus = <&sysmmu_fimd0>;

        samsung,sysreg = <&sys_reg>;

        #address-cells = <1>;

        #size-cells = <0>;

        samsung,invert-vden;

        samsung,invert-vclk;

        pinctrl-0 = <&lcd_clk>, <&lcd_data24>;

        pinctrl-names = "default";

        port@3 {

            reg = <3>;

            fimd_dpi_ep: endpoint {

                remote-endpoint = <&lcd_ep>;

            };

        };

    };