Commit e5086cb3 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Reject unsupported TMDS rates on ICL+ 

ICL+ PLLs can't genenerate certain frequencies. Running the PLL
algorithms through for all frequencies 25-594MHz we see a gap just
above 500 MHz. Specifically 500-522.8MHZ for TC PLLs, and 500-533.2
MHz for combo PHY PLLs. Reject those frequencies hdmi_port_clock_valid()
so that we properly filter out unsupported modes and/or color depths
for HDMI.

Cc: stable@vger.kernel.org
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5247


Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220311212845.32358-1-ville.syrjala@linux.intel.com


Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
parent 579899c7

drivers/gpu/drm/i915/display/intel_hdmi.c

+9 −0
Original line number Diff line number Diff line
@@ -1837,6 +1837,7 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi, 
		      bool has_hdmi_sink)

{

	struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);

	enum phy phy = intel_port_to_phy(dev_priv, hdmi_to_dig_port(hdmi)->base.port);



	if (clock < 25000)

		return MODE_CLOCK_LOW;
@@ -1857,6 +1858,14 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi, 
	if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)

		return MODE_CLOCK_RANGE;



	/* ICL+ combo PHY PLL can't generate 500-533.2 MHz */

	if (intel_phy_is_combo(dev_priv, phy) && clock > 500000 && clock < 533200)

		return MODE_CLOCK_RANGE;



	/* ICL+ TC PHY PLL can't generate 500-532.8 MHz */

	if (intel_phy_is_tc(dev_priv, phy) && clock > 500000 && clock < 532800)

		return MODE_CLOCK_RANGE;



	/*

	 * SNPS PHYs' MPLLB table-based programming can only handle a fixed

	 * set of link rates.