Commit e563531a authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915: split out intel_display_reg_defs.h 



Split out the display register helper macros to a separate file. For
now, include it from i915_reg.h, but note that there are already files
that don't need i915_reg.h, such as intel_audio.c.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/3af47193ff5219b6d2cfe353b752ec4bb44de4f1.1668008071.git.jani.nikula@intel.com
parent 81e78b13

drivers/gpu/drm/i915/display/icl_dsi_regs.h

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@@ -6,7 +6,7 @@ 
#ifndef __ICL_DSI_REGS_H__

#define __ICL_DSI_REGS_H__



#include "i915_reg_defs.h"

#include "intel_display_reg_defs.h"



/* Gen11 DSI */

#define _MMIO_DSI(tc, dsi0, dsi1)	_MMIO_TRANS((tc) - TRANSCODER_DSI_0, \

drivers/gpu/drm/i915/display/intel_audio_regs.h

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@@ -6,7 +6,7 @@ 
#ifndef __INTEL_AUDIO_REGS_H__

#define __INTEL_AUDIO_REGS_H__



#include "i915_reg_defs.h"

#include "intel_display_reg_defs.h"



#define G4X_AUD_CNTL_ST			_MMIO(0x620B4)

#define   G4X_ELD_VALID			REG_BIT(14)

drivers/gpu/drm/i915/display/intel_backlight_regs.h

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@@ -6,7 +6,7 @@ 
#ifndef __INTEL_BACKLIGHT_REGS_H__

#define __INTEL_BACKLIGHT_REGS_H__



#include "i915_reg_defs.h"

#include "intel_display_reg_defs.h"



#define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)

#define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)

drivers/gpu/drm/i915/display/intel_display_reg_defs.h

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/* SPDX-License-Identifier: MIT */

/*

 * Copyright © 2022 Intel Corporation

 */



#ifndef __INTEL_DISPLAY_REG_DEFS_H__

#define __INTEL_DISPLAY_REG_DEFS_H__



#include "i915_reg_defs.h"



#define DISPLAY_MMIO_BASE(dev_priv)	(INTEL_INFO(dev_priv)->display.mmio_offset)



#define VLV_DISPLAY_BASE		0x180000



/*

 * Named helper wrappers around _PICK_EVEN() and _PICK().

 */

#define _PIPE(pipe, a, b)		_PICK_EVEN(pipe, a, b)

#define _PLANE(plane, a, b)		_PICK_EVEN(plane, a, b)

#define _TRANS(tran, a, b)		_PICK_EVEN(tran, a, b)

#define _PORT(port, a, b)		_PICK_EVEN(port, a, b)

#define _PLL(pll, a, b)			_PICK_EVEN(pll, a, b)

#define _PHY(phy, a, b)			_PICK_EVEN(phy, a, b)



#define _MMIO_PIPE(pipe, a, b)		_MMIO(_PIPE(pipe, a, b))

#define _MMIO_PLANE(plane, a, b)	_MMIO(_PLANE(plane, a, b))

#define _MMIO_TRANS(tran, a, b)		_MMIO(_TRANS(tran, a, b))

#define _MMIO_PORT(port, a, b)		_MMIO(_PORT(port, a, b))

#define _MMIO_PLL(pll, a, b)		_MMIO(_PLL(pll, a, b))

#define _MMIO_PHY(phy, a, b)		_MMIO(_PHY(phy, a, b))



#define _PHY3(phy, ...)			_PICK(phy, __VA_ARGS__)



#define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))

#define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))

#define _MMIO_PHY3(phy, a, b, c)	_MMIO(_PHY3(phy, a, b, c))

#define _MMIO_PLL3(pll, ...)		_MMIO(_PICK(pll, __VA_ARGS__))



/*

 * Device info offset array based helpers for groups of registers with unevenly

 * spaced base offsets.

 */

#define _MMIO_PIPE2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->display.pipe_offsets[(pipe)] - \

					      INTEL_INFO(dev_priv)->display.pipe_offsets[PIPE_A] + \

					      DISPLAY_MMIO_BASE(dev_priv) + (reg))

#define _MMIO_TRANS2(tran, reg)		_MMIO(INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \

					      INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \

					      DISPLAY_MMIO_BASE(dev_priv) + (reg))

#define _MMIO_CURSOR2(pipe, reg)	_MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \

					      INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \

					      DISPLAY_MMIO_BASE(dev_priv) + (reg))



#endif /* __INTEL_DISPLAY_REG_DEFS_H__ */

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

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@@ -6,7 +6,7 @@ 
#ifndef __INTEL_HDCP_REGS_H__

#define __INTEL_HDCP_REGS_H__



#include "i915_reg_defs.h"

#include "intel_display_reg_defs.h"



/* HDCP Key Registers */

#define HDCP_KEY_CONF			_MMIO(0x66c00)