Commit e567e58d authored Nov 22, 2022 by Pierre Gondois Committed by Florian Fainelli Nov 28, 2022

arm64: dts: Update cache properties for broadcom



The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).

Update the Device Trees accordingly.

Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Link: https://lore.kernel.org/r/20221122163208.3810985-3-pierre.gondois@arm.com


Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

parent b5a17c35

arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -63,6 +63,7 @@ cpu3: cpu@3 {

		l2: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
		};
		};

arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -51,6 +51,7 @@ B53_3: cpu@3 {

		L2_0: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
		};
		};

arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -35,6 +35,7 @@ B53_1: cpu@1 {

		L2_0: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
		};
		};

arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -51,6 +51,7 @@ B53_3: cpu@3 {

		L2_0: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
		};
		};

arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -51,6 +51,7 @@ B53_3: cpu@3 {

		L2_0: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
		};
		};