Commit e5edf654 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

drm/msm/dpu: inline IRQ_n_MASK defines 



IRQ masks are rarely shared between different DPU revisions. Inline them
to the dpu_mdss_cfg intances and drop them from the dpu_hw_catalog.c

Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/530875/
Link: https://lore.kernel.org/r/20230404130622.509628-36-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent d16b77dd

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h

+8 −1
Original line number Diff line number Diff line
@@ -197,7 +197,14 @@ static const struct dpu_mdss_cfg msm8998_dpu_cfg = { 
	.vbif = msm8998_vbif,

	.reg_dma_count = 0,

	.perf = &msm8998_perf_data,

	.mdss_irqs = IRQ_SM8250_MASK,

	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \

		     BIT(MDP_SSPP_TOP0_INTR2) | \

		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \

		     BIT(MDP_INTF0_INTR) | \

		     BIT(MDP_INTF1_INTR) | \

		     BIT(MDP_INTF2_INTR) | \

		     BIT(MDP_INTF3_INTR) | \

		     BIT(MDP_INTF4_INTR),

};



#endif

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h

+9 −1
Original line number Diff line number Diff line
@@ -196,7 +196,15 @@ static const struct dpu_mdss_cfg sdm845_dpu_cfg = { 
	.reg_dma_count = 1,

	.dma_cfg = &sdm845_regdma,

	.perf = &sdm845_perf_data,

	.mdss_irqs = IRQ_SDM845_MASK,

	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \

		     BIT(MDP_SSPP_TOP0_INTR2) | \

		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \

		     BIT(MDP_INTF0_INTR) | \

		     BIT(MDP_INTF1_INTR) | \

		     BIT(MDP_INTF2_INTR) | \

		     BIT(MDP_INTF3_INTR) | \

		     BIT(MDP_AD4_0_INTR) | \

		     BIT(MDP_AD4_1_INTR),

};



#endif

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

+9 −1
Original line number Diff line number Diff line
@@ -223,7 +223,15 @@ static const struct dpu_mdss_cfg sm8150_dpu_cfg = { 
	.reg_dma_count = 1,

	.dma_cfg = &sm8150_regdma,

	.perf = &sm8150_perf_data,

	.mdss_irqs = IRQ_SDM845_MASK,

	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \

		     BIT(MDP_SSPP_TOP0_INTR2) | \

		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \

		     BIT(MDP_INTF0_INTR) | \

		     BIT(MDP_INTF1_INTR) | \

		     BIT(MDP_INTF2_INTR) | \

		     BIT(MDP_INTF3_INTR) | \

		     BIT(MDP_AD4_0_INTR) | \

		     BIT(MDP_AD4_1_INTR),

};



#endif

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

+11 −1
Original line number Diff line number Diff line
@@ -201,7 +201,17 @@ static const struct dpu_mdss_cfg sc8180x_dpu_cfg = { 
	.reg_dma_count = 1,

	.dma_cfg = &sm8150_regdma,

	.perf = &sc8180x_perf_data,

	.mdss_irqs = IRQ_SC8180X_MASK,

	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \

		     BIT(MDP_SSPP_TOP0_INTR2) | \

		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \

		     BIT(MDP_INTF0_INTR) | \

		     BIT(MDP_INTF1_INTR) | \

		     BIT(MDP_INTF2_INTR) | \

		     BIT(MDP_INTF3_INTR) | \

		     BIT(MDP_INTF4_INTR) | \

		     BIT(MDP_INTF5_INTR) | \

		     BIT(MDP_AD4_0_INTR) | \

		     BIT(MDP_AD4_1_INTR),

};



#endif

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

+8 −1
Original line number Diff line number Diff line
@@ -231,7 +231,14 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = { 
	.reg_dma_count = 1,

	.dma_cfg = &sm8250_regdma,

	.perf = &sm8250_perf_data,

	.mdss_irqs = IRQ_SM8250_MASK,

	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \

		     BIT(MDP_SSPP_TOP0_INTR2) | \

		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \

		     BIT(MDP_INTF0_INTR) | \

		     BIT(MDP_INTF1_INTR) | \

		     BIT(MDP_INTF2_INTR) | \

		     BIT(MDP_INTF3_INTR) | \

		     BIT(MDP_INTF4_INTR),

};



#endif