Commit e64d0098 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'tegra-for-5.6-dt-bindings' of... 

Merge tag 'tegra-for-5.6-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

dt-bindings: Changes for v5.6-rc1

This contains a conversion of the Tegra124 EMC bindings to json-schema
as well as the addition of the bindings for the memory subsystem found
on Tegra186 and Tegra194.

* tag 'tegra-for-5.6-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  dt-bindings: memory: Add Tegra186 memory subsystem
  dt-bindings: memory: Add Tegra194 memory controller header
  dt-bindings: memory: Add Tegra186 memory client IDs
  dt-bindings: memory-controller: Convert Tegra124 EMC to json-schema

Link: https://lore.kernel.org/r/20200111003553.2411874-1-thierry.reding@gmail.com


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 90df0360 720ad00e

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.txt

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NVIDIA Tegra124 SoC EMC (external memory controller)

====================================================



Required properties :

- compatible : Should be "nvidia,tegra124-emc".

- reg : physical base address and length of the controller's registers.

- nvidia,memory-controller : phandle of the MC driver.



The node should contain a "emc-timings" subnode for each supported RAM type

(see field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address

being its RAM_CODE.



Required properties for "emc-timings" nodes :

- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is

used for.



Each "emc-timings" node should contain a "timing" subnode for every supported

EMC clock rate. The "timing" subnodes should have the clock rate in Hz as

their unit address.



Required properties for "timing" nodes :

- clock-frequency : Should contain the memory clock rate in Hz.

- The following properties contain EMC timing characterization values

(specified in the board documentation) :

  - nvidia,emc-auto-cal-config : EMC_AUTO_CAL_CONFIG

  - nvidia,emc-auto-cal-config2 : EMC_AUTO_CAL_CONFIG2

  - nvidia,emc-auto-cal-config3 : EMC_AUTO_CAL_CONFIG3

  - nvidia,emc-auto-cal-interval : EMC_AUTO_CAL_INTERVAL

  - nvidia,emc-bgbias-ctl0 : EMC_BGBIAS_CTL0

  - nvidia,emc-cfg : EMC_CFG

  - nvidia,emc-cfg-2 : EMC_CFG_2

  - nvidia,emc-ctt-term-ctrl : EMC_CTT_TERM_CTRL

  - nvidia,emc-mode-1 : Mode Register 1

  - nvidia,emc-mode-2 : Mode Register 2

  - nvidia,emc-mode-4 : Mode Register 4

  - nvidia,emc-mode-reset : Mode Register 0

  - nvidia,emc-mrs-wait-cnt : EMC_MRS_WAIT_CNT

  - nvidia,emc-sel-dpd-ctrl : EMC_SEL_DPD_CTRL

  - nvidia,emc-xm2dqspadctrl2 : EMC_XM2DQSPADCTRL2

  - nvidia,emc-zcal-cnt-long : EMC_ZCAL_WAIT_CNT after clock change

  - nvidia,emc-zcal-interval : EMC_ZCAL_INTERVAL

- nvidia,emc-configuration : EMC timing characterization data. These are the

registers (see section "15.6.2 EMC Registers" in the TRM) whose values need to

be specified, according to the board documentation:



	EMC_RC

	EMC_RFC

	EMC_RFC_SLR

	EMC_RAS

	EMC_RP

	EMC_R2W

	EMC_W2R

	EMC_R2P

	EMC_W2P

	EMC_RD_RCD

	EMC_WR_RCD

	EMC_RRD

	EMC_REXT

	EMC_WEXT

	EMC_WDV

	EMC_WDV_MASK

	EMC_QUSE

	EMC_QUSE_WIDTH

	EMC_IBDLY

	EMC_EINPUT

	EMC_EINPUT_DURATION

	EMC_PUTERM_EXTRA

	EMC_PUTERM_WIDTH

	EMC_PUTERM_ADJ

	EMC_CDB_CNTL_1

	EMC_CDB_CNTL_2

	EMC_CDB_CNTL_3

	EMC_QRST

	EMC_QSAFE

	EMC_RDV

	EMC_RDV_MASK

	EMC_REFRESH

	EMC_BURST_REFRESH_NUM

	EMC_PRE_REFRESH_REQ_CNT

	EMC_PDEX2WR

	EMC_PDEX2RD

	EMC_PCHG2PDEN

	EMC_ACT2PDEN

	EMC_AR2PDEN

	EMC_RW2PDEN

	EMC_TXSR

	EMC_TXSRDLL

	EMC_TCKE

	EMC_TCKESR

	EMC_TPD

	EMC_TFAW

	EMC_TRPAB

	EMC_TCLKSTABLE

	EMC_TCLKSTOP

	EMC_TREFBW

	EMC_FBIO_CFG6

	EMC_ODT_WRITE

	EMC_ODT_READ

	EMC_FBIO_CFG5

	EMC_CFG_DIG_DLL

	EMC_CFG_DIG_DLL_PERIOD

	EMC_DLL_XFORM_DQS0

	EMC_DLL_XFORM_DQS1

	EMC_DLL_XFORM_DQS2

	EMC_DLL_XFORM_DQS3

	EMC_DLL_XFORM_DQS4

	EMC_DLL_XFORM_DQS5

	EMC_DLL_XFORM_DQS6

	EMC_DLL_XFORM_DQS7

	EMC_DLL_XFORM_DQS8

	EMC_DLL_XFORM_DQS9

	EMC_DLL_XFORM_DQS10

	EMC_DLL_XFORM_DQS11

	EMC_DLL_XFORM_DQS12

	EMC_DLL_XFORM_DQS13

	EMC_DLL_XFORM_DQS14

	EMC_DLL_XFORM_DQS15

	EMC_DLL_XFORM_QUSE0

	EMC_DLL_XFORM_QUSE1

	EMC_DLL_XFORM_QUSE2

	EMC_DLL_XFORM_QUSE3

	EMC_DLL_XFORM_QUSE4

	EMC_DLL_XFORM_QUSE5

	EMC_DLL_XFORM_QUSE6

	EMC_DLL_XFORM_QUSE7

	EMC_DLL_XFORM_ADDR0

	EMC_DLL_XFORM_ADDR1

	EMC_DLL_XFORM_ADDR2

	EMC_DLL_XFORM_ADDR3

	EMC_DLL_XFORM_ADDR4

	EMC_DLL_XFORM_ADDR5

	EMC_DLL_XFORM_QUSE8

	EMC_DLL_XFORM_QUSE9

	EMC_DLL_XFORM_QUSE10

	EMC_DLL_XFORM_QUSE11

	EMC_DLL_XFORM_QUSE12

	EMC_DLL_XFORM_QUSE13

	EMC_DLL_XFORM_QUSE14

	EMC_DLL_XFORM_QUSE15

	EMC_DLI_TRIM_TXDQS0

	EMC_DLI_TRIM_TXDQS1

	EMC_DLI_TRIM_TXDQS2

	EMC_DLI_TRIM_TXDQS3

	EMC_DLI_TRIM_TXDQS4

	EMC_DLI_TRIM_TXDQS5

	EMC_DLI_TRIM_TXDQS6

	EMC_DLI_TRIM_TXDQS7

	EMC_DLI_TRIM_TXDQS8

	EMC_DLI_TRIM_TXDQS9

	EMC_DLI_TRIM_TXDQS10

	EMC_DLI_TRIM_TXDQS11

	EMC_DLI_TRIM_TXDQS12

	EMC_DLI_TRIM_TXDQS13

	EMC_DLI_TRIM_TXDQS14

	EMC_DLI_TRIM_TXDQS15

	EMC_DLL_XFORM_DQ0

	EMC_DLL_XFORM_DQ1

	EMC_DLL_XFORM_DQ2

	EMC_DLL_XFORM_DQ3

	EMC_DLL_XFORM_DQ4

	EMC_DLL_XFORM_DQ5

	EMC_DLL_XFORM_DQ6

	EMC_DLL_XFORM_DQ7

	EMC_XM2CMDPADCTRL

	EMC_XM2CMDPADCTRL4

	EMC_XM2CMDPADCTRL5

	EMC_XM2DQPADCTRL2

	EMC_XM2DQPADCTRL3

	EMC_XM2CLKPADCTRL

	EMC_XM2CLKPADCTRL2

	EMC_XM2COMPPADCTRL

	EMC_XM2VTTGENPADCTRL

	EMC_XM2VTTGENPADCTRL2

	EMC_XM2VTTGENPADCTRL3

	EMC_XM2DQSPADCTRL3

	EMC_XM2DQSPADCTRL4

	EMC_XM2DQSPADCTRL5

	EMC_XM2DQSPADCTRL6

	EMC_DSR_VTTGEN_DRV

	EMC_TXDSRVTTGEN

	EMC_FBIO_SPARE

	EMC_ZCAL_WAIT_CNT

	EMC_MRS_WAIT_CNT2

	EMC_CTT

	EMC_CTT_DURATION

	EMC_CFG_PIPE

	EMC_DYN_SELF_REF_CONTROL

	EMC_QPOP



Example SoC include file:



/ {

	emc@7001b000 {

		compatible = "nvidia,tegra124-emc";

		reg = <0x0 0x7001b000 0x0 0x1000>;



		nvidia,memory-controller = <&mc>;

	};

};



Example board file:



/ {

	emc@7001b000 {

		emc-timings-3 {

			nvidia,ram-code = <3>;



			timing-12750000 {

				clock-frequency = <12750000>;



				nvidia,emc-zcal-cnt-long = <0x00000042>;

				nvidia,emc-auto-cal-interval = <0x001fffff>;

				nvidia,emc-ctt-term-ctrl = <0x00000802>;

				nvidia,emc-cfg = <0x73240000>;

				nvidia,emc-cfg-2 = <0x000008c5>;

				nvidia,emc-sel-dpd-ctrl = <0x00040128>;

				nvidia,emc-bgbias-ctl0 = <0x00000008>;

				nvidia,emc-auto-cal-config = <0xa1430000>;

				nvidia,emc-auto-cal-config2 = <0x00000000>;

				nvidia,emc-auto-cal-config3 = <0x00000000>;

				nvidia,emc-mode-reset = <0x80001221>;

				nvidia,emc-mode-1 = <0x80100003>;

				nvidia,emc-mode-2 = <0x80200008>;

				nvidia,emc-mode-4 = <0x00000000>;



				nvidia,emc-configuration = <

					0x00000000 /* EMC_RC */

					0x00000003 /* EMC_RFC */

					0x00000000 /* EMC_RFC_SLR */

					0x00000000 /* EMC_RAS */

					0x00000000 /* EMC_RP */

					0x00000004 /* EMC_R2W */

					0x0000000a /* EMC_W2R */

					0x00000003 /* EMC_R2P */

					0x0000000b /* EMC_W2P */

					0x00000000 /* EMC_RD_RCD */

					0x00000000 /* EMC_WR_RCD */

					0x00000003 /* EMC_RRD */

					0x00000003 /* EMC_REXT */

					0x00000000 /* EMC_WEXT */

					0x00000006 /* EMC_WDV */

					0x00000006 /* EMC_WDV_MASK */

					0x00000006 /* EMC_QUSE */

					0x00000002 /* EMC_QUSE_WIDTH */

					0x00000000 /* EMC_IBDLY */

					0x00000005 /* EMC_EINPUT */

					0x00000005 /* EMC_EINPUT_DURATION */

					0x00010000 /* EMC_PUTERM_EXTRA */

					0x00000003 /* EMC_PUTERM_WIDTH */

					0x00000000 /* EMC_PUTERM_ADJ */

					0x00000000 /* EMC_CDB_CNTL_1 */

					0x00000000 /* EMC_CDB_CNTL_2 */

					0x00000000 /* EMC_CDB_CNTL_3 */

					0x00000004 /* EMC_QRST */

					0x0000000c /* EMC_QSAFE */

					0x0000000d /* EMC_RDV */

					0x0000000f /* EMC_RDV_MASK */

					0x00000060 /* EMC_REFRESH */

					0x00000000 /* EMC_BURST_REFRESH_NUM */

					0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */

					0x00000002 /* EMC_PDEX2WR */

					0x00000002 /* EMC_PDEX2RD */

					0x00000001 /* EMC_PCHG2PDEN */

					0x00000000 /* EMC_ACT2PDEN */

					0x00000007 /* EMC_AR2PDEN */

					0x0000000f /* EMC_RW2PDEN */

					0x00000005 /* EMC_TXSR */

					0x00000005 /* EMC_TXSRDLL */

					0x00000004 /* EMC_TCKE */

					0x00000005 /* EMC_TCKESR */

					0x00000004 /* EMC_TPD */

					0x00000000 /* EMC_TFAW */

					0x00000000 /* EMC_TRPAB */

					0x00000005 /* EMC_TCLKSTABLE */

					0x00000005 /* EMC_TCLKSTOP */

					0x00000064 /* EMC_TREFBW */

					0x00000000 /* EMC_FBIO_CFG6 */

					0x00000000 /* EMC_ODT_WRITE */

					0x00000000 /* EMC_ODT_READ */

					0x106aa298 /* EMC_FBIO_CFG5 */

					0x002c00a0 /* EMC_CFG_DIG_DLL */

					0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */

					0x00064000 /* EMC_DLL_XFORM_DQS0 */

					0x00064000 /* EMC_DLL_XFORM_DQS1 */

					0x00064000 /* EMC_DLL_XFORM_DQS2 */

					0x00064000 /* EMC_DLL_XFORM_DQS3 */

					0x00064000 /* EMC_DLL_XFORM_DQS4 */

					0x00064000 /* EMC_DLL_XFORM_DQS5 */

					0x00064000 /* EMC_DLL_XFORM_DQS6 */

					0x00064000 /* EMC_DLL_XFORM_DQS7 */

					0x00064000 /* EMC_DLL_XFORM_DQS8 */

					0x00064000 /* EMC_DLL_XFORM_DQS9 */

					0x00064000 /* EMC_DLL_XFORM_DQS10 */

					0x00064000 /* EMC_DLL_XFORM_DQS11 */

					0x00064000 /* EMC_DLL_XFORM_DQS12 */

					0x00064000 /* EMC_DLL_XFORM_DQS13 */

					0x00064000 /* EMC_DLL_XFORM_DQS14 */

					0x00064000 /* EMC_DLL_XFORM_DQS15 */

					0x00000000 /* EMC_DLL_XFORM_QUSE0 */

					0x00000000 /* EMC_DLL_XFORM_QUSE1 */

					0x00000000 /* EMC_DLL_XFORM_QUSE2 */

					0x00000000 /* EMC_DLL_XFORM_QUSE3 */

					0x00000000 /* EMC_DLL_XFORM_QUSE4 */

					0x00000000 /* EMC_DLL_XFORM_QUSE5 */

					0x00000000 /* EMC_DLL_XFORM_QUSE6 */

					0x00000000 /* EMC_DLL_XFORM_QUSE7 */

					0x00000000 /* EMC_DLL_XFORM_ADDR0 */

					0x00000000 /* EMC_DLL_XFORM_ADDR1 */

					0x00000000 /* EMC_DLL_XFORM_ADDR2 */

					0x00000000 /* EMC_DLL_XFORM_ADDR3 */

					0x00000000 /* EMC_DLL_XFORM_ADDR4 */

					0x00000000 /* EMC_DLL_XFORM_ADDR5 */

					0x00000000 /* EMC_DLL_XFORM_QUSE8 */

					0x00000000 /* EMC_DLL_XFORM_QUSE9 */

					0x00000000 /* EMC_DLL_XFORM_QUSE10 */

					0x00000000 /* EMC_DLL_XFORM_QUSE11 */

					0x00000000 /* EMC_DLL_XFORM_QUSE12 */

					0x00000000 /* EMC_DLL_XFORM_QUSE13 */

					0x00000000 /* EMC_DLL_XFORM_QUSE14 */

					0x00000000 /* EMC_DLL_XFORM_QUSE15 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS0 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS1 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS2 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS3 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS4 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS5 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS6 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS7 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS8 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS9 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS10 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS11 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS12 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS13 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS14 */

					0x00000000 /* EMC_DLI_TRIM_TXDQS15 */

					0x000fc000 /* EMC_DLL_XFORM_DQ0 */

					0x000fc000 /* EMC_DLL_XFORM_DQ1 */

					0x000fc000 /* EMC_DLL_XFORM_DQ2 */

					0x000fc000 /* EMC_DLL_XFORM_DQ3 */

					0x0000fc00 /* EMC_DLL_XFORM_DQ4 */

					0x0000fc00 /* EMC_DLL_XFORM_DQ5 */

					0x0000fc00 /* EMC_DLL_XFORM_DQ6 */

					0x0000fc00 /* EMC_DLL_XFORM_DQ7 */

					0x10000280 /* EMC_XM2CMDPADCTRL */

					0x00000000 /* EMC_XM2CMDPADCTRL4 */

					0x00111111 /* EMC_XM2CMDPADCTRL5 */

					0x00000000 /* EMC_XM2DQPADCTRL2 */

					0x00000000 /* EMC_XM2DQPADCTRL3 */

					0x77ffc081 /* EMC_XM2CLKPADCTRL */

					0x00000e0e /* EMC_XM2CLKPADCTRL2 */

					0x81f1f108 /* EMC_XM2COMPPADCTRL */

					0x07070004 /* EMC_XM2VTTGENPADCTRL */

					0x0000003f /* EMC_XM2VTTGENPADCTRL2 */

					0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */

					0x51451400 /* EMC_XM2DQSPADCTRL3 */

					0x00514514 /* EMC_XM2DQSPADCTRL4 */

					0x00514514 /* EMC_XM2DQSPADCTRL5 */

					0x51451400 /* EMC_XM2DQSPADCTRL6 */

					0x0000003f /* EMC_DSR_VTTGEN_DRV */

					0x00000007 /* EMC_TXDSRVTTGEN */

					0x00000000 /* EMC_FBIO_SPARE */

					0x00000042 /* EMC_ZCAL_WAIT_CNT */

					0x000e000e /* EMC_MRS_WAIT_CNT2 */

					0x00000000 /* EMC_CTT */

					0x00000003 /* EMC_CTT_DURATION */

					0x0000f2f3 /* EMC_CFG_PIPE */

					0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */

					0x0000000a /* EMC_QPOP */

				>;

			};

		};

	};

};

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml

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Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NVIDIA Tegra186 (and later) SoC Memory Controller



maintainers:

  - Jon Hunter <jonathanh@nvidia.com>

  - Thierry Reding <thierry.reding@gmail.com>



description: |

  The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split

  into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC

  handles memory requests for 40-bit virtual addresses from internal clients

  and arbitrates among them to allocate memory bandwidth.



  Up to 15 GiB of physical memory can be supported. Security features such as

  encryption of traffic to and from DRAM via general security apertures are

  available for video and other secure applications, as well as DRAM ECC for

  automotive safety applications (single bit error correction and double bit

  error detection).



properties:

  $nodename:

    pattern: "^memory-controller@[0-9a-f]+$"



  compatible:

    items:

      - enum:

          - nvidia,tegra186-mc

          - nvidia,tegra194-mc



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  "#address-cells":

    const: 2



  "#size-cells":

    const: 2



  ranges: true



  dma-ranges: true



patternProperties:

  "^external-memory-controller@[0-9a-f]+$":

    description:

      The bulk of the work involved in controlling the external memory

      controller on NVIDIA Tegra186 and later is performed on the BPMP. This

      coprocessor exposes the EMC clock that is used to set the frequency at

      which the external memory is clocked and a remote procedure call that

      can be used to obtain the set of available frequencies.

    type: object

    properties:

      compatible:

        items:

          - enum:

              - nvidia,tegra186-emc

              - nvidia,tegra194-emc



      reg:

        maxItems: 1



      interrupts:

        maxItems: 1



      clocks:

        items:

          - description: external memory clock



      clock-names:

        items:

          - const: emc



      nvidia,bpmp:

        $ref: /schemas/types.yaml#/definitions/phandle

        description:

          phandle of the node representing the BPMP



required:

  - compatible

  - reg

  - interrupts

  - "#address-cells"

  - "#size-cells"



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/tegra186-clock.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    memory-controller@2c00000 {

        compatible = "nvidia,tegra186-mc";

        reg = <0x0 0x02c00000 0x0 0xb0000>;

        interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;



        #address-cells = <2>;

        #size-cells = <2>;



        ranges = <0x0 0x02c00000 0x02c00000 0x0 0xb0000>;



        /*

         * Memory clients have access to all 40 bits that the memory

         * controller can address.

         */

        dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;



        external-memory-controller@2c60000 {

            compatible = "nvidia,tegra186-emc";

            reg = <0x0 0x02c60000 0x0 0x50000>;

            interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;

            clocks = <&bpmp TEGRA186_CLK_EMC>;

            clock-names = "emc";



            nvidia,bpmp = <&bpmp>;

        };

    };



    bpmp: bpmp {

        compatible = "nvidia,tegra186-bpmp";

        #clock-cells = <1>;

    };

include/dt-bindings/memory/tegra186-mc.h

+139 −0
Original line number Diff line number Diff line
@@ -108,4 +108,143 @@ 
#define TEGRA186_SID_SE_VM6		0x4e

#define TEGRA186_SID_SE_VM7		0x4f



/*

 * memory client IDs

 */



/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */

#define TEGRA186_MEMORY_CLIENT_PTCR 0x00

/* PCIE reads */

#define TEGRA186_MEMORY_CLIENT_AFIR 0x0e

/* High-definition audio (HDA) reads */

#define TEGRA186_MEMORY_CLIENT_HDAR 0x15

/* Host channel data reads */

#define TEGRA186_MEMORY_CLIENT_HOST1XDMAR 0x16

#define TEGRA186_MEMORY_CLIENT_NVENCSRD 0x1c

/* SATA reads */

#define TEGRA186_MEMORY_CLIENT_SATAR 0x1f

/* Reads from Cortex-A9 4 CPU cores via the L2 cache */

#define TEGRA186_MEMORY_CLIENT_MPCORER 0x27

#define TEGRA186_MEMORY_CLIENT_NVENCSWR 0x2b

/* PCIE writes */

#define TEGRA186_MEMORY_CLIENT_AFIW 0x31

/* High-definition audio (HDA) writes */

#define TEGRA186_MEMORY_CLIENT_HDAW 0x35

/* Writes from Cortex-A9 4 CPU cores via the L2 cache */

#define TEGRA186_MEMORY_CLIENT_MPCOREW 0x39

/* SATA writes */

#define TEGRA186_MEMORY_CLIENT_SATAW 0x3d

/* ISP Read client for Crossbar A */

#define TEGRA186_MEMORY_CLIENT_ISPRA 0x44

/* ISP Write client for Crossbar A */

#define TEGRA186_MEMORY_CLIENT_ISPWA 0x46

/* ISP Write client Crossbar B */

#define TEGRA186_MEMORY_CLIENT_ISPWB 0x47

/* XUSB reads */

#define TEGRA186_MEMORY_CLIENT_XUSB_HOSTR 0x4a

/* XUSB_HOST writes */

#define TEGRA186_MEMORY_CLIENT_XUSB_HOSTW 0x4b

/* XUSB reads */

#define TEGRA186_MEMORY_CLIENT_XUSB_DEVR 0x4c

/* XUSB_DEV writes */

#define TEGRA186_MEMORY_CLIENT_XUSB_DEVW 0x4d

/* TSEC Memory Return Data Client Description */

#define TEGRA186_MEMORY_CLIENT_TSECSRD 0x54

/* TSEC Memory Write Client Description */

#define TEGRA186_MEMORY_CLIENT_TSECSWR 0x55

/* 3D, ltcx reads instance 0 */

#define TEGRA186_MEMORY_CLIENT_GPUSRD 0x58

/* 3D, ltcx writes instance 0 */

#define TEGRA186_MEMORY_CLIENT_GPUSWR 0x59

/* sdmmca memory read client */

#define TEGRA186_MEMORY_CLIENT_SDMMCRA 0x60

/* sdmmcbmemory read client */

#define TEGRA186_MEMORY_CLIENT_SDMMCRAA 0x61

/* sdmmc memory read client */

#define TEGRA186_MEMORY_CLIENT_SDMMCR 0x62

/* sdmmcd memory read client */

#define TEGRA186_MEMORY_CLIENT_SDMMCRAB 0x63

/* sdmmca memory write client */

#define TEGRA186_MEMORY_CLIENT_SDMMCWA 0x64

/* sdmmcb memory write client */

#define TEGRA186_MEMORY_CLIENT_SDMMCWAA 0x65

/* sdmmc memory write client */

#define TEGRA186_MEMORY_CLIENT_SDMMCW 0x66

/* sdmmcd memory write client */

#define TEGRA186_MEMORY_CLIENT_SDMMCWAB 0x67

#define TEGRA186_MEMORY_CLIENT_VICSRD 0x6c

#define TEGRA186_MEMORY_CLIENT_VICSWR 0x6d

/* VI Write client */

#define TEGRA186_MEMORY_CLIENT_VIW 0x72

#define TEGRA186_MEMORY_CLIENT_NVDECSRD 0x78

#define TEGRA186_MEMORY_CLIENT_NVDECSWR 0x79

/* Audio Processing (APE) engine reads */

#define TEGRA186_MEMORY_CLIENT_APER 0x7a

/* Audio Processing (APE) engine writes */

#define TEGRA186_MEMORY_CLIENT_APEW 0x7b

#define TEGRA186_MEMORY_CLIENT_NVJPGSRD 0x7e

#define TEGRA186_MEMORY_CLIENT_NVJPGSWR 0x7f

/* SE Memory Return Data Client Description */

#define TEGRA186_MEMORY_CLIENT_SESRD 0x80

/* SE Memory Write Client Description */

#define TEGRA186_MEMORY_CLIENT_SESWR 0x81

/* ETR reads */

#define TEGRA186_MEMORY_CLIENT_ETRR 0x84

/* ETR writes */

#define TEGRA186_MEMORY_CLIENT_ETRW 0x85

/* TSECB Memory Return Data Client Description */

#define TEGRA186_MEMORY_CLIENT_TSECSRDB 0x86

/* TSECB Memory Write Client Description */

#define TEGRA186_MEMORY_CLIENT_TSECSWRB 0x87

/* 3D, ltcx reads instance 1 */

#define TEGRA186_MEMORY_CLIENT_GPUSRD2 0x88

/* 3D, ltcx writes instance 1 */

#define TEGRA186_MEMORY_CLIENT_GPUSWR2 0x89

/* AXI Switch read client */

#define TEGRA186_MEMORY_CLIENT_AXISR 0x8c

/* AXI Switch write client */

#define TEGRA186_MEMORY_CLIENT_AXISW 0x8d

/* EQOS read client */

#define TEGRA186_MEMORY_CLIENT_EQOSR 0x8e

/* EQOS write client */

#define TEGRA186_MEMORY_CLIENT_EQOSW 0x8f

/* UFSHC read client */

#define TEGRA186_MEMORY_CLIENT_UFSHCR 0x90

/* UFSHC write client */

#define TEGRA186_MEMORY_CLIENT_UFSHCW 0x91

/* NVDISPLAY read client */

#define TEGRA186_MEMORY_CLIENT_NVDISPLAYR 0x92

/* BPMP read client */

#define TEGRA186_MEMORY_CLIENT_BPMPR 0x93

/* BPMP write client */

#define TEGRA186_MEMORY_CLIENT_BPMPW 0x94

/* BPMPDMA read client */

#define TEGRA186_MEMORY_CLIENT_BPMPDMAR 0x95

/* BPMPDMA write client */

#define TEGRA186_MEMORY_CLIENT_BPMPDMAW 0x96

/* AON read client */

#define TEGRA186_MEMORY_CLIENT_AONR 0x97

/* AON write client */

#define TEGRA186_MEMORY_CLIENT_AONW 0x98

/* AONDMA read client */

#define TEGRA186_MEMORY_CLIENT_AONDMAR 0x99

/* AONDMA write client */

#define TEGRA186_MEMORY_CLIENT_AONDMAW 0x9a

/* SCE read client */

#define TEGRA186_MEMORY_CLIENT_SCER 0x9b

/* SCE write client */

#define TEGRA186_MEMORY_CLIENT_SCEW 0x9c

/* SCEDMA read client */

#define TEGRA186_MEMORY_CLIENT_SCEDMAR 0x9d

/* SCEDMA write client */

#define TEGRA186_MEMORY_CLIENT_SCEDMAW 0x9e

/* APEDMA read client */

#define TEGRA186_MEMORY_CLIENT_APEDMAR 0x9f

/* APEDMA write client */

#define TEGRA186_MEMORY_CLIENT_APEDMAW 0xa0

/* NVDISPLAY read client instance 2 */

#define TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 0xa1

#define TEGRA186_MEMORY_CLIENT_VICSRD1 0xa2

#define TEGRA186_MEMORY_CLIENT_NVDECSRD1 0xa3



#endif

include/dt-bindings/memory/tegra194-mc.h

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