Commit e663e06b authored by Anand Gore's avatar Anand Gore Committed by Florian Fainelli
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ARM64: dts: Add DTS files for bcmbca SoC BCM6858 



Add DTS for ARMv8 based broadband SoC BCM6858. bcm6858.dtsi is the SoC
description DTS header and bcm96858.dts is a simple DTS file for
Broadcom BCM96858 Reference board that only enables the UART port.

Signed-off-by: default avatarAnand Gore <anand.gore@broadcom.com>
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
parent 1ba56aeb

arch/arm64/boot/dts/broadcom/bcmbca/Makefile

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# SPDX-License-Identifier: GPL-2.0

dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \

				bcm963158.dtb
 
				bcm963158.dtb \

				bcm96858.dtb

arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Copyright 2022 Broadcom Ltd.

 */



#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	compatible = "brcm,bcm6858", "brcm,bcmbca";

	#address-cells = <2>;

	#size-cells = <2>;



	interrupt-parent = <&gic>;



	cpus {

		#address-cells = <2>;

		#size-cells = <0>;



		B53_0: cpu@0 {

			compatible = "brcm,brahma-b53";

			device_type = "cpu";

			reg = <0x0 0x0>;

			next-level-cache = <&L2_0>;

			enable-method = "psci";

		};



		B53_1: cpu@1 {

			compatible = "brcm,brahma-b53";

			device_type = "cpu";

			reg = <0x0 0x1>;

			next-level-cache = <&L2_0>;

			enable-method = "psci";

		};



		B53_2: cpu@2 {

			compatible = "brcm,brahma-b53";

			device_type = "cpu";

			reg = <0x0 0x2>;

			next-level-cache = <&L2_0>;

			enable-method = "psci";

		};



		B53_3: cpu@3 {

			compatible = "brcm,brahma-b53";

			device_type = "cpu";

			reg = <0x0 0x3>;

			next-level-cache = <&L2_0>;

			enable-method = "psci";

		};

		L2_0: l2-cache0 {

			compatible = "cache";

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

	};



	pmu: pmu {

		compatible = "arm,armv8-pmuv3";

		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-affinity = <&B53_0>, <&B53_1>,

			<&B53_2>, <&B53_3>;

	};



	clocks: clocks {

		periph_clk:periph-clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <200000000>;

		};

	};



	psci {

		compatible = "arm,psci-0.2";

		method = "smc";

	};



	axi@81000000 {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x0 0x0 0x81000000 0x8000>;



		gic: interrupt-controller@1000 {

			compatible = "arm,gic-400";

			#interrupt-cells = <3>;

			interrupt-controller;

			reg = <0x1000 0x1000>, /* GICD */

				<0x2000 0x2000>, /* GICC */

				<0x4000 0x2000>, /* GICH */

				<0x6000 0x2000>; /* GICV */

			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |

					IRQ_TYPE_LEVEL_HIGH)>;

		};

	};



	bus@ff800000 {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x0 0x0 0xff800000 0x62000>;



		uart0: serial@640 {

			compatible = "brcm,bcm6345-uart";

			reg = <0x640 0x18>;

			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&periph_clk>;

			clock-names = "refclk";

			status = "disabled";

		};

	};

};

arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Copyright 2022 Broadcom Ltd.

 */



/dts-v1/;



#include "bcm6858.dtsi"



/ {

	model = "Broadcom BCM96858 Reference Board";

	compatible = "brcm,bcm96858", "brcm,bcm6858", "brcm,bcmbca";



	aliases {

		serial0 = &uart0;

	};



	chosen {

		stdout-path = "serial0:115200n8";

	};



	memory@0 {

		device_type = "memory";

		reg = <0x0 0x0 0x0 0x08000000>;

	};

};



&uart0 {

	status = "okay";

};