Commit e6b69813 authored by Manivannan Sadhasivam's avatar Manivannan Sadhasivam Committed by Bjorn Andersson
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ARM: dts: qcom: sdx55: Add support for PCIe EP 



Add support for PCIe Endpoint controller on the Qualcomm SDX55 platform.

Signed-off-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211126070520.28979-4-manivannan.sadhasivam@linaro.org
parent a5a26612

arch/arm/boot/dts/qcom-sdx55.dtsi

+45 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 


#include <dt-bindings/clock/qcom,gcc-sdx55.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/interconnect/qcom,sdx55.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/power/qcom-rpmpd.h>
@@ -391,6 +392,11 @@ tcsr_mutex: hwlock@1f40000 { 
			#hwlock-cells = <1>;

		};



		tcsr: syscon@1fcb000 {

			compatible = "syscon";

			reg = <0x01fc0000 0x1000>;

		};



		sdhc_1: sdhci@8804000 {

			compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";

			reg = <0x08804000 0x1000>;
@@ -403,6 +409,45 @@ sdhc_1: sdhci@8804000 { 
			status = "disabled";

		};



		pcie_ep: pcie-ep@40000000 {

			compatible = "qcom,sdx55-pcie-ep";

			reg = <0x01c00000 0x3000>,

			      <0x40000000 0xf1d>,

			      <0x40000f20 0xc8>,

			      <0x40001000 0x1000>,

			      <0x40002000 0x10000>,

			      <0x01c03000 0x3000>;

			reg-names = "parf", "dbi", "elbi", "atu", "addr_space",

				    "mmio";



			qcom,perst-regs = <&tcsr 0xb258 0xb270>;



			clocks = <&gcc GCC_PCIE_AUX_CLK>,

				 <&gcc GCC_PCIE_CFG_AHB_CLK>,

				 <&gcc GCC_PCIE_MSTR_AXI_CLK>,

				 <&gcc GCC_PCIE_SLV_AXI_CLK>,

				 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,

				 <&gcc GCC_PCIE_SLEEP_CLK>,

				 <&gcc GCC_PCIE_0_CLKREF_CLK>;

			clock-names = "aux", "cfg", "bus_master", "bus_slave",

				      "slave_q2a", "sleep", "ref";



			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "global", "doorbell";

			reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;

			wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;

			resets = <&gcc GCC_PCIE_BCR>;

			reset-names = "core";

			power-domains = <&gcc PCIE_GDSC>;

			phys = <&pcie0_lane>;

			phy-names = "pciephy";

			max-link-speed = <3>;

			num-lanes = <2>;



			status = "disabled";

		};



		remoteproc_mpss: remoteproc@4080000 {

			compatible = "qcom,sdx55-mpss-pas";

			reg = <0x04080000 0x4040>;