Commit e7145aae authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: enable dcn315/316 s0i2 support 



[why]
enable the support in driver, let the control by CMOS

Reviewed-by: default avatarAric Cyr <Aric.Cyr@amd.com>
Acked-by: default avatarAlan Liu <HaoPing.Liu@amd.com>
Signed-off-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4185f990

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -131,6 +131,7 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base, 
				union display_idle_optimization_u idle_info = { 0 };

				union display_idle_optimization_u idle_info = { 0 };

				idle_info.idle_info.df_request_disabled = 1;

				idle_info.idle_info.df_request_disabled = 1;

				idle_info.idle_info.phy_ref_clk_off = 1;

				idle_info.idle_info.phy_ref_clk_off = 1;

				idle_info.idle_info.s0i2_rdy = 1;

				dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data);

				dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data);

				/* update power state */

				/* update power state */

				clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;

				clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
@@ -526,7 +527,6 @@ void dcn315_clk_mgr_construct( 
		struct dccg *dccg)

		struct dccg *dccg)

{

{

	struct dcn315_smu_dpm_clks smu_dpm_clks = { 0 };

	struct dcn315_smu_dpm_clks smu_dpm_clks = { 0 };

	struct clk_mgr *clk_mgr_base = ctx->dc->clk_mgr;





	clk_mgr->base.base.ctx = ctx;

	clk_mgr->base.base.ctx = ctx;

	clk_mgr->base.base.funcs = &dcn315_funcs;

	clk_mgr->base.base.funcs = &dcn315_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

+1 −2
Original line number Original line Diff line number Diff line
@@ -172,8 +172,7 @@ static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base, 
				union display_idle_optimization_u idle_info = { 0 };

				union display_idle_optimization_u idle_info = { 0 };

				idle_info.idle_info.df_request_disabled = 1;

				idle_info.idle_info.df_request_disabled = 1;

				idle_info.idle_info.phy_ref_clk_off = 1;

				idle_info.idle_info.phy_ref_clk_off = 1;

				// Todo DCN316 set this to 1 if any no issue

				idle_info.idle_info.s0i2_rdy = 1;

				idle_info.idle_info.s0i2_rdy = 0;

				dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data);

				dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data);

				/* update power state */

				/* update power state */

				clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;

				clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;