Commit e94ee641 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'edac_updates_for_v6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras 

Pull EDAC updates from Borislav Petkov:

 - skx_edac: Fix overflow when decoding 32G DIMM ranks

 - i10nm_edac: Add Sierra Forest support

 - amd64_edac: Split driver code between legacy and SMCA systems. The
   final goal is adding support for more hw, like GPUs

 - The usual minor cleanups and fixes

* tag 'edac_updates_for_v6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras: (25 commits)
  EDAC/i10nm: Add Intel Sierra Forest server support
  EDAC/amd64: Fix indentation in umc_determine_edac_cap()
  EDAC/altera: Remove MODULE_LICENSE in non-module
  EDAC: Sanitize MODULE_AUTHOR strings
  EDAC/amd81[13]1: Remove trailing newline from MODULE_AUTHOR
  EDAC/amd64: Add get_err_info() to pvt->ops
  EDAC/amd64: Split dump_misc_regs() into dct/umc functions
  EDAC/amd64: Split init_csrows() into dct/umc functions
  EDAC/amd64: Split determine_edac_cap() into dct/umc functions
  EDAC/amd64: Rename f17h_determine_edac_ctl_cap()
  EDAC/amd64: Split setup_mci_misc_attrs() into dct/umc functions
  EDAC/amd64: Split ecc_enabled() into dct/umc functions
  EDAC/amd64: Split read_mc_regs() into dct/umc functions
  EDAC/amd64: Split determine_memory_type() into dct/umc functions
  EDAC/amd64: Split read_base_mask() into dct/umc functions
  EDAC/amd64: Split prep_chip_selects() into dct/umc functions
  EDAC/amd64: Rework hw_info_{get,put}
  EDAC/amd64: Merge struct amd64_family_type into struct amd64_pvt
  EDAC/amd64: Do not discover ECC symbol size for Family 17h and later
  EDAC/amd64: Drop dbam_to_cs() for Family 17h and later
  ...
parents f7301270 ce8ac911

drivers/edac/altera_edac.c

+3 −7
Original line number Diff line number Diff line
@@ -2149,10 +2149,8 @@ static int altr_edac_a10_probe(struct platform_device *pdev) 
	}



	edac->sb_irq = platform_get_irq(pdev, 0);

	if (edac->sb_irq < 0) {

		dev_err(&pdev->dev, "No SBERR IRQ resource\n");

	if (edac->sb_irq < 0)

		return edac->sb_irq;

	}



	irq_set_chained_handler_and_data(edac->sb_irq,

					 altr_edac_a10_irq_handler,
@@ -2184,10 +2182,9 @@ static int altr_edac_a10_probe(struct platform_device *pdev) 
	}

#else

	edac->db_irq = platform_get_irq(pdev, 1);

	if (edac->db_irq < 0) {

		dev_err(&pdev->dev, "No DBERR IRQ resource\n");

	if (edac->db_irq < 0)

		return edac->db_irq;

	}



	irq_set_chained_handler_and_data(edac->db_irq,

					 altr_edac_a10_irq_handler, edac);

#endif
@@ -2226,6 +2223,5 @@ static struct platform_driver altr_edac_a10_driver = { 
};

module_platform_driver(altr_edac_a10_driver);



MODULE_LICENSE("GPL v2");

MODULE_AUTHOR("Thor Thayer");

MODULE_DESCRIPTION("EDAC Driver for Altera Memories");

drivers/edac/amd64_edac.c

+447 −573

File changed.

Preview size limit exceeded, changes collapsed.

drivers/edac/amd64_edac.h

+25 −42
Original line number Diff line number Diff line
@@ -273,25 +273,6 @@ 


#define UMC_SDP_INIT			BIT(31)



enum amd_families {

	K8_CPUS = 0,

	F10_CPUS,

	F15_CPUS,

	F15_M30H_CPUS,

	F15_M60H_CPUS,

	F16_CPUS,

	F16_M30H_CPUS,

	F17_CPUS,

	F17_M10H_CPUS,

	F17_M30H_CPUS,

	F17_M60H_CPUS,

	F17_M70H_CPUS,

	F19_CPUS,

	F19_M10H_CPUS,

	F19_M50H_CPUS,

	NUM_FAMILIES,

};



/* Error injection control structure */

struct error_injection {

	u32	 section;
@@ -334,6 +315,16 @@ struct amd64_umc { 
	enum mem_type dram_type;

};



struct amd64_family_flags {

	/*

	 * Indicates that the system supports the new register offsets, etc.

	 * first introduced with Family 19h Model 10h.

	 */

	__u64 zn_regs_v2	: 1,



	      __reserved	: 63;

};



struct amd64_pvt {

	struct low_ops *ops;
@@ -375,6 +366,12 @@ struct amd64_pvt { 
	/* x4, x8, or x16 syndromes in use */

	u8 ecc_sym_sz;



	const char *ctl_name;

	u16 f1_id, f2_id;

	/* Maximum number of memory controllers per die/node. */

	u8 max_mcs;



	struct amd64_family_flags flags;

	/* place to store error injection parameters prior to issue */

	struct error_injection injection;
@@ -466,28 +463,14 @@ struct ecc_settings { 
 */

struct low_ops {

	void (*map_sysaddr_to_csrow)(struct mem_ctl_info *mci, u64 sys_addr,

					 struct err_info *);

				     struct err_info *err);

	int  (*dbam_to_cs)(struct amd64_pvt *pvt, u8 dct,

					 unsigned cs_mode, int cs_mask_nr);

};



struct amd64_family_flags {

	/*

	 * Indicates that the system supports the new register offsets, etc.

	 * first introduced with Family 19h Model 10h.

	 */

	__u64 zn_regs_v2	: 1,



	      __reserved	: 63;

};



struct amd64_family_type {

	const char *ctl_name;

	u16 f1_id, f2_id;

	/* Maximum number of memory controllers per die/node. */

	u8 max_mcs;

	struct amd64_family_flags flags;

	struct low_ops ops;

			   unsigned int cs_mode, int cs_mask_nr);

	int (*hw_info_get)(struct amd64_pvt *pvt);

	bool (*ecc_enabled)(struct amd64_pvt *pvt);

	void (*setup_mci_misc_attrs)(struct mem_ctl_info *mci);

	void (*dump_misc_regs)(struct amd64_pvt *pvt);

	void (*get_err_info)(struct mce *m, struct err_info *err);

};



int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,

drivers/edac/amd8111_edac.c

+1 −1
Original line number Diff line number Diff line
@@ -593,5 +593,5 @@ module_init(amd8111_edac_init); 
module_exit(amd8111_edac_exit);



MODULE_LICENSE("GPL");

MODULE_AUTHOR("Cao Qingtao <qingtao.cao@windriver.com>\n");

MODULE_AUTHOR("Cao Qingtao <qingtao.cao@windriver.com>");

MODULE_DESCRIPTION("AMD8111 HyperTransport I/O Hub EDAC kernel module");

drivers/edac/amd8131_edac.c

+1 −1
Original line number Diff line number Diff line
@@ -354,5 +354,5 @@ module_init(amd8131_edac_init); 
module_exit(amd8131_edac_exit);



MODULE_LICENSE("GPL");

MODULE_AUTHOR("Cao Qingtao <qingtao.cao@windriver.com>\n");

MODULE_AUTHOR("Cao Qingtao <qingtao.cao@windriver.com>");

MODULE_DESCRIPTION("AMD8131 HyperTransport PCI-X Tunnel EDAC kernel module");