Loading drivers/gpu/drm/nouveau/include/nvif/cl0080.h +4 −0 Original line number Diff line number Diff line Loading @@ -57,6 +57,7 @@ struct nv_device_time_v0 { #define NV_DEVICE_INFO_UNIT (0xffffffffULL << 32) #define NV_DEVICE_INFO(n) ((n) | (0x00000000ULL << 32)) #define NV_DEVICE_FIFO(n) ((n) | (0x00000001ULL << 32)) /* This will be returned for unsupported queries. */ #define NV_DEVICE_INFO_INVALID ~0ULL Loading @@ -79,4 +80,7 @@ struct nv_device_time_v0 { #define NV_DEVICE_INFO_ENGINE_SEC2 NV_DEVICE_INFO(0x0000000e) #define NV_DEVICE_INFO_ENGINE_NVDEC NV_DEVICE_INFO(0x0000000f) #define NV_DEVICE_INFO_ENGINE_NVENC NV_DEVICE_INFO(0x00000010) /* Returns the number of available channels. */ #define NV_DEVICE_FIFO_CHANNELS NV_DEVICE_FIFO(0x00000000) #endif drivers/gpu/drm/nouveau/include/nvif/device.h +0 −1 Original line number Diff line number Diff line Loading @@ -67,6 +67,5 @@ u64 nvif_device_time(struct nvif_device *); #include <engine/fifo.h> #include <engine/gr.h> #define nvxx_fifo(a) nvxx_device(a)->fifo #define nvxx_gr(a) nvxx_device(a)->gr #endif drivers/gpu/drm/nouveau/nouveau_chan.c +25 −0 Original line number Diff line number Diff line Loading @@ -474,3 +474,28 @@ nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device, cli->base.super = super; return ret; } int nouveau_channels_init(struct nouveau_drm *drm) { struct { struct nv_device_info_v1 m; struct { struct nv_device_info_v1_data channels; } v; } args = { .m.version = 1, .m.count = sizeof(args.v) / sizeof(args.v.channels), .v.channels.mthd = NV_DEVICE_FIFO_CHANNELS, }; struct nvif_object *device = &drm->client.device.object; int ret; ret = nvif_object_mthd(device, NV_DEVICE_V0_INFO, &args, sizeof(args)); if (ret || args.v.channels.mthd == NV_DEVICE_INFO_INVALID) return -ENODEV; drm->chan.nr = args.v.channels.data; drm->chan.context_base = dma_fence_context_alloc(drm->chan.nr); return 0; } drivers/gpu/drm/nouveau/nouveau_chan.h +1 −0 Original line number Diff line number Diff line Loading @@ -45,6 +45,7 @@ struct nouveau_channel { atomic_t killed; }; int nouveau_channels_init(struct nouveau_drm *); int nouveau_channel_new(struct nouveau_drm *, struct nvif_device *, u32 arg0, u32 arg1, struct nouveau_channel **); Loading drivers/gpu/drm/nouveau/nouveau_drm.c +4 −0 Original line number Diff line number Diff line Loading @@ -307,6 +307,10 @@ nouveau_accel_init(struct nouveau_drm *drm) if (nouveau_noaccel) return; ret = nouveau_channels_init(drm); if (ret) return; /* initialise synchronisation routines */ /*XXX: this is crap, but the fence/channel stuff is a little * backwards in some places. this will be fixed. Loading Loading
drivers/gpu/drm/nouveau/include/nvif/cl0080.h +4 −0 Original line number Diff line number Diff line Loading @@ -57,6 +57,7 @@ struct nv_device_time_v0 { #define NV_DEVICE_INFO_UNIT (0xffffffffULL << 32) #define NV_DEVICE_INFO(n) ((n) | (0x00000000ULL << 32)) #define NV_DEVICE_FIFO(n) ((n) | (0x00000001ULL << 32)) /* This will be returned for unsupported queries. */ #define NV_DEVICE_INFO_INVALID ~0ULL Loading @@ -79,4 +80,7 @@ struct nv_device_time_v0 { #define NV_DEVICE_INFO_ENGINE_SEC2 NV_DEVICE_INFO(0x0000000e) #define NV_DEVICE_INFO_ENGINE_NVDEC NV_DEVICE_INFO(0x0000000f) #define NV_DEVICE_INFO_ENGINE_NVENC NV_DEVICE_INFO(0x00000010) /* Returns the number of available channels. */ #define NV_DEVICE_FIFO_CHANNELS NV_DEVICE_FIFO(0x00000000) #endif
drivers/gpu/drm/nouveau/include/nvif/device.h +0 −1 Original line number Diff line number Diff line Loading @@ -67,6 +67,5 @@ u64 nvif_device_time(struct nvif_device *); #include <engine/fifo.h> #include <engine/gr.h> #define nvxx_fifo(a) nvxx_device(a)->fifo #define nvxx_gr(a) nvxx_device(a)->gr #endif
drivers/gpu/drm/nouveau/nouveau_chan.c +25 −0 Original line number Diff line number Diff line Loading @@ -474,3 +474,28 @@ nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device, cli->base.super = super; return ret; } int nouveau_channels_init(struct nouveau_drm *drm) { struct { struct nv_device_info_v1 m; struct { struct nv_device_info_v1_data channels; } v; } args = { .m.version = 1, .m.count = sizeof(args.v) / sizeof(args.v.channels), .v.channels.mthd = NV_DEVICE_FIFO_CHANNELS, }; struct nvif_object *device = &drm->client.device.object; int ret; ret = nvif_object_mthd(device, NV_DEVICE_V0_INFO, &args, sizeof(args)); if (ret || args.v.channels.mthd == NV_DEVICE_INFO_INVALID) return -ENODEV; drm->chan.nr = args.v.channels.data; drm->chan.context_base = dma_fence_context_alloc(drm->chan.nr); return 0; }
drivers/gpu/drm/nouveau/nouveau_chan.h +1 −0 Original line number Diff line number Diff line Loading @@ -45,6 +45,7 @@ struct nouveau_channel { atomic_t killed; }; int nouveau_channels_init(struct nouveau_drm *); int nouveau_channel_new(struct nouveau_drm *, struct nvif_device *, u32 arg0, u32 arg1, struct nouveau_channel **); Loading
drivers/gpu/drm/nouveau/nouveau_drm.c +4 −0 Original line number Diff line number Diff line Loading @@ -307,6 +307,10 @@ nouveau_accel_init(struct nouveau_drm *drm) if (nouveau_noaccel) return; ret = nouveau_channels_init(drm); if (ret) return; /* initialise synchronisation routines */ /*XXX: this is crap, but the fence/channel stuff is a little * backwards in some places. this will be fixed. Loading