Commit ebbb0b10 authored by Srinivasan Shanmugam's avatar Srinivasan Shanmugam Committed by Alex Deucher
Browse files

drm/amd/display: Clean up dcn10_optc.c kdoc 



Fixes the following W=1 kernel build warning:

display/dc/dcn10/dcn10_optc.c:45: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* apply_front_porch_workaround  TODO FPGA still need?
display/dc/dcn10/dcn10_optc.c:136: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
 * program_timing_generator   used by mode timing set
display/dc/dcn10/dcn10_optc.c:391: warning: Function parameter or member 'optc' not described in 'optc1_set_timing_double_buffer'
display/dc/dcn10/dcn10_optc.c:391: warning: Function parameter or member 'enable' not described in 'optc1_set_timing_double_buffer'
display/dc/dcn10/dcn10_optc.c:404: warning: Function parameter or member 'optc' not described in 'optc1_unblank_crtc'
display/dc/dcn10/dcn10_optc.c:404: warning: expecting prototype for unblank_crtc(). Prototype was for optc1_unblank_crtc() instead
display/dc/dcn10/dcn10_optc.c:427: warning: Function parameter or member 'optc' not described in 'optc1_blank_crtc'
display/dc/dcn10/dcn10_optc.c:427: warning: expecting prototype for blank_crtc(). Prototype was for optc1_blank_crtc() instead
display/dc/dcn10/dcn10_optc.c:496: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
 * Enable CRTC
display/dc/dcn10/dcn10_optc.c:895: warning: Cannot understand  *****************************************************************************
 on line 895 - I thought it was a doc line

Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarSrinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2e1e62c8

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c

+36 −21
Original line number Diff line number Diff line
@@ -42,10 +42,12 @@ 
#define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100



/**

* apply_front_porch_workaround  TODO FPGA still need?

 * apply_front_porch_workaround() - This is a workaround for a bug that has

 *                                  existed since R5xx and has not been fixed

 *                                  keep Front porch at minimum 2 for Interlaced

 *                                  mode or 1 for progressive.

 *

* This is a workaround for a bug that has existed since R5xx and has not been

* fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.

 * @timing: Timing parameters used to configure DCN blocks.

 */

static void apply_front_porch_workaround(struct dc_crtc_timing *timing)

{
@@ -133,9 +135,20 @@ void optc1_setup_vertical_interrupt2( 
}



/**

 * program_timing_generator   used by mode timing set

 * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition.

 * optc1_program_timing() - used by mode timing set Program

 *                          CRTC Timing Registers - OTG_H_*,

 *                          OTG_V_*, Pixel repetition.

 *                          Including SYNC. Call BIOS command table to program Timings.

 *

 * @optc: timing_generator instance.

 * @dc_crtc_timing: Timing parameters used to configure DCN blocks.

 * @vready_offset: Vready's starting position.

 * @vstartup_start: Vstartup period.

 * @vupdate_offset: Vupdate starting position.

 * @vupdate_width: Vupdate duration.

 * @signal: DC signal types.

 * @use_vbios: to program timings from BIOS command table.

 *

 */

void optc1_program_timing(

	struct timing_generator *optc,
@@ -385,6 +398,9 @@ void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enab 
 * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN,

 * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers.

 *

 * @optc: timing_generator instance.

 * @enable: Enable DRR double buffering control if true, disable otherwise.

 *

 * Options: any time,  start of frame, dp start of frame (range timing)

 */

void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable)
@@ -397,8 +413,9 @@ void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable) 
}



/**

 * unblank_crtc

 * Call ASIC Control Object to UnBlank CRTC.

 * optc1_unblank_crtc() - Call ASIC Control Object to UnBlank CRTC.

 *

 * @optc: timing_generator instance.

 */

static void optc1_unblank_crtc(struct timing_generator *optc)

{
@@ -419,8 +436,9 @@ static void optc1_unblank_crtc(struct timing_generator *optc) 
}



/**

 * blank_crtc

 * Call ASIC Control Object to Blank CRTC.

 * optc1_blank_crtc() - Call ASIC Control Object to Blank CRTC.

 *

 * @optc: timing_generator instance.

 */



static void optc1_blank_crtc(struct timing_generator *optc)
@@ -493,8 +511,9 @@ void optc1_enable_optc_clock(struct timing_generator *optc, bool enable) 
}



/**

 * Enable CRTC

 * Enable CRTC - call ASIC Control Object to enable Timing generator.

 * optc1_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator.

 *

 * @optc: timing_generator instance.

 */

static bool optc1_enable_crtc(struct timing_generator *optc)

{
@@ -890,15 +909,11 @@ static void optc1_program_manual_trigger(struct timing_generator *optc) 
			MANUAL_FLOW_CONTROL, 0);

}





/**

 *****************************************************************************

 *  Function: set_drr

 * optc1_set_drr() - Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.

 *

 *  @brief

 *     Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.

 *

 *****************************************************************************

 * @optc: timing_generator instance.

 * @params: parameters used for Dynamic Refresh Rate.

 */

void optc1_set_drr(

	struct timing_generator *optc,