Commit ed34855b authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
Browse files

ARM: tegra: cardhu: Support CPU frequency and voltage scaling on all board variants 



Enable CPU frequency and voltage scaling on all Tegra30 Cardhu board
variants.

Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 3744c7d8

arch/arm/boot/dts/tegra30-cardhu-a04.dts

+0 −48
Original line number Diff line number Diff line
@@ -2,8 +2,6 @@ 
/dts-v1/;



#include "tegra30-cardhu.dtsi"

#include "tegra30-cpu-opp.dtsi"

#include "tegra30-cpu-opp-microvolt.dtsi"



/* This dts file support the cardhu A04 and later versions of board */
@@ -92,50 +90,4 @@ vdd_bl2_reg: regulator@106 { 
		enable-active-high;

		gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;

	};



	i2c@7000d000 {

		pmic: tps65911@2d {

			regulators {

				vddctrl_reg: vddctrl {

					regulator-min-microvolt = <800000>;

					regulator-max-microvolt = <1125000>;

					regulator-coupled-with = <&vddcore_reg>;

					regulator-coupled-max-spread = <300000>;

					regulator-max-step-microvolt = <100000>;



					nvidia,tegra-cpu-regulator;

				};

			};

		};



		vddcore_reg: tps62361@60 {

			regulator-coupled-with = <&vddctrl_reg>;

			regulator-coupled-max-spread = <300000>;

			regulator-max-step-microvolt = <100000>;



			nvidia,tegra-core-regulator;

		};

	};



	cpus {

		cpu0: cpu@0 {

			cpu-supply = <&vddctrl_reg>;

			operating-points-v2 = <&cpu0_opp_table>;

		};



		cpu@1 {

			cpu-supply = <&vddctrl_reg>;

			operating-points-v2 = <&cpu0_opp_table>;

		};



		cpu@2 {

			cpu-supply = <&vddctrl_reg>;

			operating-points-v2 = <&cpu0_opp_table>;

		};



		cpu@3 {

			cpu-supply = <&vddctrl_reg>;

			operating-points-v2 = <&cpu0_opp_table>;

		};

	};

};

arch/arm/boot/dts/tegra30-cardhu.dtsi

+37 −3
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

#include <dt-bindings/input/input.h>

#include "tegra30.dtsi"

#include "tegra30-cpu-opp.dtsi"

#include "tegra30-cpu-opp-microvolt.dtsi"



/**

 * This file contains common DT entry for all fab version of Cardhu.
@@ -272,9 +274,14 @@ vdd2_reg: vdd2 { 


				vddctrl_reg: vddctrl {

					regulator-name = "vdd_cpu,vdd_sys";

					regulator-min-microvolt = <1000000>;

					regulator-max-microvolt = <1000000>;

					regulator-min-microvolt = <800000>;

					regulator-max-microvolt = <1250000>;

					regulator-coupled-with = <&vdd_core>;

					regulator-coupled-max-spread = <300000>;

					regulator-max-step-microvolt = <100000>;

					regulator-always-on;



					nvidia,tegra-cpu-regulator;

				};



				vio_reg: vio {
@@ -342,17 +349,22 @@ temperature-sensor@4c { 
			interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;

		};



		tps62361@60 {

		vdd_core: tps62361@60 {

			compatible = "ti,tps62361";

			reg = <0x60>;



			regulator-name = "tps62361-vout";

			regulator-min-microvolt = <500000>;

			regulator-max-microvolt = <1500000>;

			regulator-coupled-with = <&vddctrl_reg>;

			regulator-coupled-max-spread = <300000>;

			regulator-max-step-microvolt = <100000>;

			regulator-boot-on;

			regulator-always-on;

			ti,vsel0-state-high;

			ti,vsel1-state-high;



			nvidia,tegra-core-regulator;

		};

	};
@@ -424,6 +436,28 @@ clk32k_in: clock@0 { 
		#clock-cells = <0>;

	};



	cpus {

		cpu0: cpu@0 {

			cpu-supply = <&vddctrl_reg>;

			operating-points-v2 = <&cpu0_opp_table>;

		};



		cpu1: cpu@1 {

			cpu-supply = <&vddctrl_reg>;

			operating-points-v2 = <&cpu0_opp_table>;

		};



		cpu2: cpu@2 {

			cpu-supply = <&vddctrl_reg>;

			operating-points-v2 = <&cpu0_opp_table>;

		};



		cpu3: cpu@3 {

			cpu-supply = <&vddctrl_reg>;

			operating-points-v2 = <&cpu0_opp_table>;

		};

	};



	panel: panel {

		compatible = "chunghwa,claa101wb01";

		ddc-i2c-bus = <&panelddc>;