Commit edeba49e authored by Rafael J. Wysocki's avatar Rafael J. Wysocki
Browse files

Merge tag 'cpufreq-arm-updates-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm 

Pull cpufreq ARM updates for 6.2 from Viresh Kumar:

"- Generalize of_perf_domain_get_sharing_cpumask phandle format (Hector
   Martin).

 - New cpufreq driver for Apple SoC CPU P-states (Hector Martin).

 - Lots of Qualcomm cpufreq driver updates, that include CPU clock
   provider support, generic cleanups or reorganization, fixed a
   potential memleak and the return value of cpufreq_driver->get()
   (Manivannan Sadhasivam, and Chen Hui).

 - Few updates to Qualcomm cpufreq driver's DT bindings, that include
   support for CPU clock provider, fixing missing cache related
   properties, and support for QDU1000/QRU1000 (Manivannan Sadhasivam,
   Rob Herring, and Melody Olvera).

 - Add support for ti,am625 SoC and enable build of ti-cpufreq for
   ARCH_K3 (Dave Gerlach, and Vibhore Vardhan).

 - tegra186: Use flexible array to simplify memory allocation (Christophe
   JAILLET)."

* tag 'cpufreq-arm-updates-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm:
  dt-bindings: cpufreq: cpufreq-qcom-hw: Add QDU1000/QRU1000 cpufreq
  cpufreq: tegra186: Use flexible array to simplify memory allocation
  cpufreq: apple-soc: Add new driver to control Apple SoC CPU P-states
  cpufreq: qcom-hw: Add CPU clock provider support
  dt-bindings: cpufreq: cpufreq-qcom-hw: Add cpufreq clock provider
  cpufreq: qcom-hw: Fix the frequency returned by cpufreq_driver->get()
  cpufreq: qcom-hw: Fix memory leak in qcom_cpufreq_hw_read_lut()
  arm64: dts: ti: k3-am625-sk: Add 1.4GHz OPP
  cpufreq: ti: Enable ti-cpufreq for ARCH_K3
  arm64: dts: ti: k3-am625: Introduce operating-points table
  cpufreq: dt-platdev: Blacklist ti,am625 SoC
  cpufreq: ti-cpufreq: Add support for AM625
  dt-bindings: cpufreq: qcom: Add missing cache related properties
  cpufreq: qcom-hw: Move soc_data to struct qcom_cpufreq
  cpufreq: qcom-hw: Use cached dev pointer in probe()
  cpufreq: qcom-hw: Allocate qcom_cpufreq_data during probe
  cpufreq: qcom-hw: Remove un-necessary cpumask_empty() check
  cpufreq: Generalize of_perf_domain_get_sharing_cpumask phandle format
parents df51f287 8ff150aa

Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml

+31 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ properties: 
      - description: v2 of CPUFREQ HW (EPSS)

        items:

          - enum:

              - qcom,qdu1000-cpufreq-epss

              - qcom,sm6375-cpufreq-epss

              - qcom,sm8250-cpufreq-epss

          - const: qcom,cpufreq-epss
@@ -56,6 +57,9 @@ properties: 
  '#freq-domain-cells':

    const: 1



  '#clock-cells':

    const: 1



required:

  - compatible

  - reg
@@ -83,11 +87,16 @@ examples: 
        enable-method = "psci";

        next-level-cache = <&L2_0>;

        qcom,freq-domain = <&cpufreq_hw 0>;

        clocks = <&cpufreq_hw 0>;

        L2_0: l2-cache {

          compatible = "cache";

          cache-unified;

          cache-level = <2>;

          next-level-cache = <&L3_0>;

          L3_0: l3-cache {

            compatible = "cache";

            cache-unified;

            cache-level = <3>;

          };

        };

      };
@@ -99,8 +108,11 @@ examples: 
        enable-method = "psci";

        next-level-cache = <&L2_100>;

        qcom,freq-domain = <&cpufreq_hw 0>;

        clocks = <&cpufreq_hw 0>;

        L2_100: l2-cache {

          compatible = "cache";

          cache-unified;

          cache-level = <2>;

          next-level-cache = <&L3_0>;

        };

      };
@@ -112,8 +124,11 @@ examples: 
        enable-method = "psci";

        next-level-cache = <&L2_200>;

        qcom,freq-domain = <&cpufreq_hw 0>;

        clocks = <&cpufreq_hw 0>;

        L2_200: l2-cache {

          compatible = "cache";

          cache-unified;

          cache-level = <2>;

          next-level-cache = <&L3_0>;

        };

      };
@@ -125,8 +140,11 @@ examples: 
        enable-method = "psci";

        next-level-cache = <&L2_300>;

        qcom,freq-domain = <&cpufreq_hw 0>;

        clocks = <&cpufreq_hw 0>;

        L2_300: l2-cache {

          compatible = "cache";

          cache-unified;

          cache-level = <2>;

          next-level-cache = <&L3_0>;

        };

      };
@@ -138,8 +156,11 @@ examples: 
        enable-method = "psci";

        next-level-cache = <&L2_400>;

        qcom,freq-domain = <&cpufreq_hw 1>;

        clocks = <&cpufreq_hw 1>;

        L2_400: l2-cache {

          compatible = "cache";

          cache-unified;

          cache-level = <2>;

          next-level-cache = <&L3_0>;

        };

      };
@@ -151,8 +172,11 @@ examples: 
        enable-method = "psci";

        next-level-cache = <&L2_500>;

        qcom,freq-domain = <&cpufreq_hw 1>;

        clocks = <&cpufreq_hw 1>;

        L2_500: l2-cache {

          compatible = "cache";

          cache-unified;

          cache-level = <2>;

          next-level-cache = <&L3_0>;

        };

      };
@@ -164,8 +188,11 @@ examples: 
        enable-method = "psci";

        next-level-cache = <&L2_600>;

        qcom,freq-domain = <&cpufreq_hw 1>;

        clocks = <&cpufreq_hw 1>;

        L2_600: l2-cache {

          compatible = "cache";

          cache-unified;

          cache-level = <2>;

          next-level-cache = <&L3_0>;

        };

      };
@@ -177,8 +204,11 @@ examples: 
        enable-method = "psci";

        next-level-cache = <&L2_700>;

        qcom,freq-domain = <&cpufreq_hw 1>;

        clocks = <&cpufreq_hw 1>;

        L2_700: l2-cache {

          compatible = "cache";

          cache-unified;

          cache-level = <2>;

          next-level-cache = <&L3_0>;

        };

      };
@@ -197,6 +227,7 @@ examples: 
        clock-names = "xo", "alternate";



        #freq-domain-cells = <1>;

        #clock-cells = <1>;

      };

    };

...

arch/arm64/boot/dts/ti/k3-am625-sk.dts

+9 −0
Original line number Diff line number Diff line
@@ -31,6 +31,15 @@ chosen { 
		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";

	};



	opp-table {

		/* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */

		opp-1400000000 {

			opp-hz = /bits/ 64 <1400000000>;

			opp-supported-hw = <0x01 0x0004>;

			clock-latency-ns = <6000000>;

		};

	};



	memory@80000000 {

		device_type = "memory";

		/* 2G RAM */

arch/arm64/boot/dts/ti/k3-am625.dtsi

+51 −0
Original line number Diff line number Diff line
@@ -48,6 +48,8 @@ cpu0: cpu@0 { 
			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&L2_0>;

			operating-points-v2 = <&a53_opp_table>;

			clocks = <&k3_clks 135 0>;

		};



		cpu1: cpu@1 {
@@ -62,6 +64,8 @@ cpu1: cpu@1 { 
			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&L2_0>;

			operating-points-v2 = <&a53_opp_table>;

			clocks = <&k3_clks 136 0>;

		};



		cpu2: cpu@2 {
@@ -76,6 +80,8 @@ cpu2: cpu@2 { 
			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&L2_0>;

			operating-points-v2 = <&a53_opp_table>;

			clocks = <&k3_clks 137 0>;

		};



		cpu3: cpu@3 {
@@ -90,6 +96,51 @@ cpu3: cpu@3 { 
			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&L2_0>;

			operating-points-v2 = <&a53_opp_table>;

			clocks = <&k3_clks 138 0>;

		};

	};



	a53_opp_table: opp-table {

		compatible = "operating-points-v2-ti-cpu";

		opp-shared;

		syscon = <&wkup_conf>;



		opp-200000000 {

			opp-hz = /bits/ 64 <200000000>;

			opp-supported-hw = <0x01 0x0007>;

			clock-latency-ns = <6000000>;

		};



		opp-400000000 {

			opp-hz = /bits/ 64 <400000000>;

			opp-supported-hw = <0x01 0x0007>;

			clock-latency-ns = <6000000>;

		};



		opp-600000000 {

			opp-hz = /bits/ 64 <600000000>;

			opp-supported-hw = <0x01 0x0007>;

			clock-latency-ns = <6000000>;

		};



		opp-800000000 {

			opp-hz = /bits/ 64 <800000000>;

			opp-supported-hw = <0x01 0x0007>;

			clock-latency-ns = <6000000>;

		};



		opp-1000000000 {

			opp-hz = /bits/ 64 <1000000000>;

			opp-supported-hw = <0x01 0x0006>;

			clock-latency-ns = <6000000>;

		};



		opp-1250000000 {

			opp-hz = /bits/ 64 <1250000000>;

			opp-supported-hw = <0x01 0x0004>;

			clock-latency-ns = <6000000>;

			opp-suspend;

		};

	};

drivers/cpufreq/Kconfig.arm

+11 −2
Original line number Diff line number Diff line
@@ -41,6 +41,15 @@ config ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM 
	  To compile this driver as a module, choose M here: the

	  module will be called sun50i-cpufreq-nvmem.



config ARM_APPLE_SOC_CPUFREQ

	tristate "Apple Silicon SoC CPUFreq support"

	depends on ARCH_APPLE || (COMPILE_TEST && 64BIT)

	select PM_OPP

	default ARCH_APPLE

	help

	  This adds the CPUFreq driver for Apple Silicon machines

	  (e.g. Apple M1).



config ARM_ARMADA_37XX_CPUFREQ

	tristate "Armada 37xx CPUFreq support"

	depends on ARCH_MVEBU && CPUFREQ_DT
@@ -340,8 +349,8 @@ config ARM_TEGRA194_CPUFREQ 


config ARM_TI_CPUFREQ

	bool "Texas Instruments CPUFreq support"

	depends on ARCH_OMAP2PLUS

	default ARCH_OMAP2PLUS

	depends on ARCH_OMAP2PLUS || ARCH_K3

	default y

	help

	  This driver enables valid OPPs on the running platform based on

	  values contained within the SoC in use. Enable this in order to

drivers/cpufreq/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ obj-$(CONFIG_X86_AMD_FREQ_SENSITIVITY) += amd_freq_sensitivity.o 


##################################################################################

# ARM SoC drivers

obj-$(CONFIG_ARM_APPLE_SOC_CPUFREQ)	+= apple-soc-cpufreq.o

obj-$(CONFIG_ARM_ARMADA_37XX_CPUFREQ)	+= armada-37xx-cpufreq.o

obj-$(CONFIG_ARM_ARMADA_8K_CPUFREQ)	+= armada-8k-cpufreq.o

obj-$(CONFIG_ARM_BRCMSTB_AVS_CPUFREQ)	+= brcmstb-avs-cpufreq.o