Commit edec7bbb authored by James Courtier-Dutton's avatar James Courtier-Dutton Committed by Jaroslav Kysela
Browse files

[ALSA] snd-emu10k1:Support for ADAT and S/PDIF. 



Patch submitted by Ctirad Fertr
<c.fertr@volny.cz>

Signed-off-by: default avatarJames Courtier-Dutton <James@superbug.co.uk>
Signed-off-by: default avatarJaroslav Kysela <perex@suse.cz>
parent aaccf54f

sound/pci/emu10k1/emu10k1_main.c

+3 −3
Original line number Diff line number Diff line
@@ -872,8 +872,8 @@ static int snd_emu10k1_emu1010_init(struct snd_emu10k1 * emu) 
	snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &reg );

	snd_printk(KERN_INFO "emu1010: Card options=0x%x\n",reg);

	snd_emu1010_fpga_read(emu, EMU_HANA_OPTICAL_TYPE, &tmp ); 

	/* ADAT input. */

	snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, 0x01 );

	/* Optical -> ADAT I/O  */

	snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, EMU_HANA_OPTICAL_IN_ADAT | EMU_HANA_OPTICAL_OUT_ADAT );

	snd_emu1010_fpga_read(emu, EMU_HANA_ADC_PADS, &tmp );

	/* Set no attenuation on Audio Dock pads. */

	snd_emu1010_fpga_write(emu, EMU_HANA_ADC_PADS, 0x00 );
@@ -1150,7 +1150,7 @@ static int snd_emu10k1_emu1010_init(struct snd_emu10k1 * emu) 
	emu->emu1010.output_source[23] = 28;



	/* TEMP: Select SPDIF in/out */

	snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, 0x0); /* Output spdif */

	//snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, 0x0); /* Output spdif */



	/* TEMP: Select 48kHz SPDIF out */

	snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x0); /* Mute all */

sound/pci/emu10k1/emumixer.c

+46 −6
Original line number Diff line number Diff line
@@ -501,17 +501,19 @@ static struct snd_kcontrol_new snd_emu1010_dac_pads[] __devinitdata = { 
static int snd_emu1010_internal_clock_info(struct snd_kcontrol *kcontrol,

					  struct snd_ctl_elem_info *uinfo)

{

	static char *texts[2] = {

		"44100", "48000"

	static char *texts[4] = {

		"44100", "48000", "SPDIF", "ADAT"

	};

		

	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;

	uinfo->count = 1;

	uinfo->value.enumerated.items = 2;

	if (uinfo->value.enumerated.item > 1)

                uinfo->value.enumerated.item = 1;

	uinfo->value.enumerated.items = 4;

	if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)

		uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;

	strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);

	return 0;

	

	

}



static int snd_emu1010_internal_clock_get(struct snd_kcontrol *kcontrol,
@@ -568,6 +570,44 @@ static int snd_emu1010_internal_clock_put(struct snd_kcontrol *kcontrol, 
			msleep(10);

			/* Unmute all */

			snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE );

			break;

			

		case 2: /* Take clock from S/PDIF IN */

			/* Mute all */

			snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_MUTE );

			/* Default fallback clock 48kHz */

			snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, EMU_HANA_DEFCLOCK_48K );

			/* Word Clock source, sync to S/PDIF input */

			snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK,

				EMU_HANA_WCLOCK_HANA_SPDIF_IN | EMU_HANA_WCLOCK_1X );

			/* Set LEDs on Audio Dock */

			snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2,

				EMU_HANA_DOCK_LEDS_2_EXT | EMU_HANA_DOCK_LEDS_2_LOCK );

			/* FIXME: We should set EMU_HANA_DOCK_LEDS_2_LOCK only when clock signal is present and valid */	

			/* Allow DLL to settle */

			msleep(10);

			/* Unmute all */

			snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE );

			break;

		

		case 3: 			

			/* Take clock from ADAT IN */

			/* Mute all */

			snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_MUTE );

			/* Default fallback clock 48kHz */

			snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, EMU_HANA_DEFCLOCK_48K );

			/* Word Clock source, sync to ADAT input */

			snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK,

				EMU_HANA_WCLOCK_HANA_ADAT_IN | EMU_HANA_WCLOCK_1X );

			/* Set LEDs on Audio Dock */

			snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, EMU_HANA_DOCK_LEDS_2_EXT | EMU_HANA_DOCK_LEDS_2_LOCK );

			/* FIXME: We should set EMU_HANA_DOCK_LEDS_2_LOCK only when clock signal is present and valid */	

			/* Allow DLL to settle */

			msleep(10);

			/*   Unmute all */

			snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE );

			 

			

			break;		

		}

	}