Commit eef4344f authored by James Morse's avatar James Morse Committed by Will Deacon
Browse files

arm64/sysreg: Standardise naming for ID_ISAR6_EL1 



To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.

Ensure symbols for the ID_ISAR6_EL1 register have an _EL1 suffix.

No functional change.

Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-8-james.morse@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 816c8638

arch/arm64/include/asm/sysreg.h

+7 −7
Original line number Diff line number Diff line
@@ -725,13 +725,13 @@ 
#define ID_ISAR5_EL1_AES_SHIFT		4

#define ID_ISAR5_EL1_SEVL_SHIFT		0



#define ID_ISAR6_I8MM_SHIFT		24

#define ID_ISAR6_BF16_SHIFT		20

#define ID_ISAR6_SPECRES_SHIFT		16

#define ID_ISAR6_SB_SHIFT		12

#define ID_ISAR6_FHM_SHIFT		8

#define ID_ISAR6_DP_SHIFT		4

#define ID_ISAR6_JSCVT_SHIFT		0

#define ID_ISAR6_EL1_I8MM_SHIFT		24

#define ID_ISAR6_EL1_BF16_SHIFT		20

#define ID_ISAR6_EL1_SPECRES_SHIFT	16

#define ID_ISAR6_EL1_SB_SHIFT		12

#define ID_ISAR6_EL1_FHM_SHIFT		8

#define ID_ISAR6_EL1_DP_SHIFT		4

#define ID_ISAR6_EL1_JSCVT_SHIFT	0



#define ID_MMFR0_EL1_InnerShr_SHIFT	28

#define ID_MMFR0_EL1_FCSE_SHIFT		24

arch/arm64/kernel/cpufeature.c

+7 −7
Original line number Diff line number Diff line
@@ -527,13 +527,13 @@ static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 
};



static const struct arm64_ftr_bits ftr_id_isar6[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0),

	ARM64_FTR_END,

};