Commit eff5e115 authored by Wenjing Liu's avatar Wenjing Liu Committed by Alex Deucher
Browse files

drm/amd/display: extract set stream attribute to link_hwss 



[why]
Extract set stream attribute into link_hwss as part of the link hwss
refactor work.

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: default avatarGeorge Shen <George.Shen@amd.com>
Acked-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3f689345

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+9 −47
Original line number Diff line number Diff line
@@ -4123,6 +4123,7 @@ void core_link_enable_stream( 
	struct link_encoder *link_enc;

	enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;

	struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;

	const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);



	if (is_dp_128b_132b_signal(pipe_ctx))

		vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
@@ -4151,56 +4152,19 @@ void core_link_enable_stream( 
			link_enc->funcs->setup(

				link_enc,

				pipe_ctx->stream->signal);

		pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(

			pipe_ctx->stream_res.stream_enc,

			pipe_ctx->stream_res.tg->inst,

			stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);

	}



	if (is_dp_128b_132b_signal(pipe_ctx)) {

		pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->set_stream_attribute(

				pipe_ctx->stream_res.hpo_dp_stream_enc,

				&stream->timing,

				stream->output_color_space,

				stream->use_vsc_sdp_for_colorimetry,

				stream->timing.flags.DSC,

				false);

		otg_out_dest = OUT_MUX_HPO_DP;

	} else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

		pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(

				pipe_ctx->stream_res.stream_enc,

				&stream->timing,

				stream->output_color_space,

				stream->use_vsc_sdp_for_colorimetry,

				stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);

	}



	if (dc_is_dp_signal(pipe_ctx->stream->signal))

		dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DP_STREAM_ATTR);



	if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))

		pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(

			pipe_ctx->stream_res.stream_enc,

			&stream->timing,

			stream->phy_pix_clk,

			pipe_ctx->stream_res.audio != NULL);



	pipe_ctx->stream->link->link_state_valid = true;



	if (pipe_ctx->stream_res.tg->funcs->set_out_mux)

	if (pipe_ctx->stream_res.tg->funcs->set_out_mux) {

		if (is_dp_128b_132b_signal(pipe_ctx))

			otg_out_dest = OUT_MUX_HPO_DP;

		else

			otg_out_dest = OUT_MUX_DIO;

		pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);

	}



	if (dc_is_dvi_signal(pipe_ctx->stream->signal))

		pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(

			pipe_ctx->stream_res.stream_enc,

			&stream->timing,

			(pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?

			true : false);



	if (dc_is_lvds_signal(pipe_ctx->stream->signal))

		pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(

			pipe_ctx->stream_res.stream_enc,

			&stream->timing);

	link_hwss->setup_stream_attribute(pipe_ctx);



	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {

		bool apply_edp_fast_boot_optimization =
@@ -4335,13 +4299,11 @@ void core_link_enable_stream( 
		dc->hwss.enable_audio_stream(pipe_ctx);



	} else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))

		if (is_dp_128b_132b_signal(pipe_ctx)) {

		if (is_dp_128b_132b_signal(pipe_ctx))

			fpga_dp_hpo_enable_link_and_stream(state, pipe_ctx);

		}

		if (dc_is_dp_signal(pipe_ctx->stream->signal) ||

				dc_is_virtual_signal(pipe_ctx->stream->signal))

			dp_set_dsc_enable(pipe_ctx, true);



	}



	if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h

+1 −0
Original line number Diff line number Diff line
@@ -72,6 +72,7 @@ struct link_hwss { 
	 */

	void (*setup_stream_encoder)(struct pipe_ctx *pipe_ctx);

	void (*reset_stream_encoder)(struct pipe_ctx *pipe_ctx);

	void (*setup_stream_attribute)(struct pipe_ctx *pipe_ctx);

};

#endif /* __DC_LINK_HWSS_H__ */

drivers/gpu/drm/amd/display/dc/link/link_hwss_dio.c

+41 −0
Original line number Diff line number Diff line
@@ -62,6 +62,46 @@ void reset_dio_stream_encoder(struct pipe_ctx *pipe_ctx) 


}



void setup_dio_stream_attribute(struct pipe_ctx *pipe_ctx)

{

	struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;

	struct dc_stream_state *stream = pipe_ctx->stream;

	struct dc_link *link = stream->link;



	if (!dc_is_virtual_signal(stream->signal))

		stream_encoder->funcs->setup_stereo_sync(

				stream_encoder,

				pipe_ctx->stream_res.tg->inst,

				stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);



	if (dc_is_dp_signal(stream->signal))

		stream_encoder->funcs->dp_set_stream_attribute(

				stream_encoder,

				&stream->timing,

				stream->output_color_space,

				stream->use_vsc_sdp_for_colorimetry,

				link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);

	else if (dc_is_hdmi_tmds_signal(stream->signal))

		stream_encoder->funcs->hdmi_set_stream_attribute(

				stream_encoder,

				&stream->timing,

				stream->phy_pix_clk,

				pipe_ctx->stream_res.audio != NULL);

	else if (dc_is_dvi_signal(stream->signal))

		stream_encoder->funcs->dvi_set_stream_attribute(

				stream_encoder,

				&stream->timing,

				(stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?

						true : false);

	else if (dc_is_lvds_signal(stream->signal))

		stream_encoder->funcs->lvds_set_stream_attribute(

				stream_encoder,

				&stream->timing);



	if (dc_is_dp_signal(stream->signal))

		dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DP_STREAM_ATTR);

}



void enable_dio_dp_link_output(struct dc_link *link,

		const struct link_resource *link_res,

		enum signal_type signal,
@@ -116,6 +156,7 @@ void set_dio_dp_lane_settings(struct dc_link *link, 
static const struct link_hwss dio_link_hwss = {

	.setup_stream_encoder = setup_dio_stream_encoder,

	.reset_stream_encoder = reset_dio_stream_encoder,

	.setup_stream_attribute = setup_dio_stream_attribute,

	.ext = {

		.set_throttled_vcp_size = set_dio_throttled_vcp_size,

		.enable_dp_link_output = enable_dio_dp_link_output,

drivers/gpu/drm/amd/display/dc/link/link_hwss_dio.h

+1 −0
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ void set_dio_throttled_vcp_size(struct pipe_ctx *pipe_ctx, 
		struct fixed31_32 throttled_vcp_size);

void setup_dio_stream_encoder(struct pipe_ctx *pipe_ctx);

void reset_dio_stream_encoder(struct pipe_ctx *pipe_ctx);

void setup_dio_stream_attribute(struct pipe_ctx *pipe_ctx);

void enable_dio_dp_link_output(struct dc_link *link,

		const struct link_resource *link_res,

		enum signal_type signal,

drivers/gpu/drm/amd/display/dc/link/link_hwss_dpia.c

+1 −0
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ 
static const struct link_hwss dpia_link_hwss = {

	.setup_stream_encoder = setup_dio_stream_encoder,

	.reset_stream_encoder = reset_dio_stream_encoder,

	.setup_stream_attribute = setup_dio_stream_attribute,

	.ext = {

		.set_throttled_vcp_size = set_dio_throttled_vcp_size,

		.enable_dp_link_output = enable_dio_dp_link_output,