Commit f16c3236 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events: Update metrics for HaswellX 

Based on TMA_metrics-full.csv version 4.3 at 01.org:
    https://download.01.org/perfmon/
Events are updated to version 22:
    https://download.01.org/perfmon/HSX
Json files generated by:
    https://github.com/intel/event-converter-for-linux-perf



Tested:

  ...
    6: Parse event definition strings                                  : Ok
    7: Simple expression parser                                        : Ok
  ...
    9: Parse perf pmu format                                           : Ok
   10: PMU events                                                      :
   10.1: PMU event table sanity                                        : Ok
   10.2: PMU event map aliases                                         : Ok
   10.3: Parsing of PMU event table metrics                            : Ok
   10.4: Parsing of PMU event table metrics with fake PMUs             : Ok
  ...
   68: Parse and process metrics                                       : Ok
  ...
   88: perf stat metrics (shadow stat) test                            : Ok
   89: perf all metricgroups test                                      : Ok
   90: perf all metrics test                                           : FAILED!
   91: perf all PMU test                                               : Ok
  ...

Test 90 failed for Load_Miss_Real_Latency with <not counted> events:

 Performance counter stats for 'system wide':

     <not counted>      mem_load_uops_retired.hit_lfb                                     (0.00%)
     <not counted>      MEM_LOAD_UOPS_RETIRED.L1_MISS                                     (0.00%)
     <not counted>      L1D_PEND_MISS.PENDING                                         (0.00%)
       1002638743 ns   duration_time

This is exposing a somewhat known issue with weak groups that can
be worked around with:

$ perf stat --metric-no-group -M Load_Miss_Real_Latency -a sleep 1

 Performance counter stats for 'system wide':

           9539883      mem_load_uops_retired.hit_lfb #    25.87 Load_Miss_Real_Latency   (83.24%)
          10876212      MEM_LOAD_UOPS_RETIRED.L1_MISS                                     (66.68%)
         528172960      L1D_PEND_MISS.PENDING                                         (83.26%)
        1001964165 ns   duration_time

Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20220201015858.1226914-6-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 49898fef

tools/perf/pmu-events/arch/x86/haswellx/cache.json

+717 −717

File changed.

Preview size limit exceeded, changes collapsed.

tools/perf/pmu-events/arch/x86/haswellx/floating-point.json

+68 −48
Original line number Diff line number Diff line 
[

    {

        "EventCode": "0xC1",

        "UMask": "0x8",

        "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",

        "BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores.  May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.",

        "Counter": "0,1,2,3",

        "EventName": "OTHER_ASSISTS.AVX_TO_SSE",

        "Errata": "HSD56, HSM57",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xC6",

        "EventName": "AVX_INSTS.ALL",

        "PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.",

        "SampleAfterValue": "2000003",

        "UMask": "0x7"

    },

    {

        "EventCode": "0xC1",

        "UMask": "0x10",

        "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",

        "BriefDescription": "Cycles with any input/output SSE or FP assist",

        "Counter": "0,1,2,3",

        "EventName": "OTHER_ASSISTS.SSE_TO_AVX",

        "Errata": "HSD56, HSM57",

        "CounterHTOff": "0,1,2,3",

        "CounterMask": "1",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.ANY",

        "PublicDescription": "Cycles with any input/output SSE* or FP assists.",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x1e"

    },

    {

        "EventCode": "0xC6",

        "UMask": "0x7",

        "BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores.  May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.",

        "BriefDescription": "Number of SIMD FP assists due to input values",

        "Counter": "0,1,2,3",

        "EventName": "AVX_INSTS.ALL",

        "PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.SIMD_INPUT",

        "PublicDescription": "Number of SIMD FP assists due to input values.",

        "SampleAfterValue": "100003",

        "UMask": "0x10"

    },

    {

        "EventCode": "0xCA",

        "UMask": "0x2",

        "BriefDescription": "Number of X87 assists due to output value.",

        "BriefDescription": "Number of SIMD FP assists due to Output values",

        "Counter": "0,1,2,3",

        "EventName": "FP_ASSIST.X87_OUTPUT",

        "PublicDescription": "Number of X87 FP assists due to output values.",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.SIMD_OUTPUT",

        "PublicDescription": "Number of SIMD FP assists due to output values.",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x8"

    },

    {

        "EventCode": "0xCA",

        "UMask": "0x4",

        "BriefDescription": "Number of X87 assists due to input value.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.X87_INPUT",

        "PublicDescription": "Number of X87 FP assists due to input values.",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x4"

    },

    {

        "EventCode": "0xCA",

        "UMask": "0x8",

        "BriefDescription": "Number of SIMD FP assists due to Output values",

        "BriefDescription": "Number of X87 assists due to output value.",

        "Counter": "0,1,2,3",

        "EventName": "FP_ASSIST.SIMD_OUTPUT",

        "PublicDescription": "Number of SIMD FP assists due to output values.",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.X87_OUTPUT",

        "PublicDescription": "Number of X87 FP assists due to output values.",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x2"

    },

    {

        "EventCode": "0xCA",

        "UMask": "0x10",

        "BriefDescription": "Number of SIMD FP assists due to input values",

        "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",

        "Counter": "0,1,2,3",

        "EventName": "FP_ASSIST.SIMD_INPUT",

        "PublicDescription": "Number of SIMD FP assists due to input values.",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x58",

        "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",

        "PublicDescription": "Number of SIMD move elimination candidate uops that were eliminated.",

        "SampleAfterValue": "1000003",

        "UMask": "0x2"

    },

    {

        "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x58",

        "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",

        "PublicDescription": "Number of SIMD move elimination candidate uops that were not eliminated.",

        "SampleAfterValue": "1000003",

        "UMask": "0x8"

    },

    {

        "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "Errata": "HSD56, HSM57",

        "EventCode": "0xC1",

        "EventName": "OTHER_ASSISTS.AVX_TO_SSE",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x8"

    },

    {

        "EventCode": "0xCA",

        "UMask": "0x1e",

        "BriefDescription": "Cycles with any input/output SSE or FP assist",

        "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",

        "Counter": "0,1,2,3",

        "EventName": "FP_ASSIST.ANY",

        "CounterMask": "1",

        "PublicDescription": "Cycles with any input/output SSE* or FP assists.",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "Errata": "HSD56, HSM57",

        "EventCode": "0xC1",

        "EventName": "OTHER_ASSISTS.SSE_TO_AVX",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3"

        "UMask": "0x10"

    }

]
 
 No newline at end of file

tools/perf/pmu-events/arch/x86/haswellx/frontend.json

+173 −163

File changed.

Preview size limit exceeded, changes collapsed.

tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json

+136 −127

File changed.

Preview size limit exceeded, changes collapsed.

tools/perf/pmu-events/arch/x86/haswellx/memory.json

+539 −531

File changed.

Preview size limit exceeded, changes collapsed.