Commit f1f923ad authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Vinod Koul
Browse files

phy: qcom-qmp: move QSERDES V5 registers to separate headers 



Move QSERDES V5 registers to the separate headers.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220705094320.1313312-12-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 32d2cf53

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h

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/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (c) 2017, The Linux Foundation. All rights reserved.

 */



#ifndef QCOM_PHY_QMP_QSERDES_COM_V5_H_

#define QCOM_PHY_QMP_QSERDES_COM_V5_H_



/* Only for QMP V5 PHY - QSERDES COM registers */

#define QSERDES_V5_COM_SSC_EN_CENTER			0x010

#define QSERDES_V5_COM_SSC_PER1				0x01c

#define QSERDES_V5_COM_SSC_PER2				0x020

#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0		0x024

#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0		0x028

#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1		0x030

#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1		0x034

#define QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN		0x044

#define QSERDES_V5_COM_CLK_ENABLE1			0x048

#define QSERDES_V5_COM_SYSCLK_BUF_ENABLE		0x050

#define QSERDES_V5_COM_PLL_IVCO				0x058

#define QSERDES_V5_COM_CP_CTRL_MODE0			0x074

#define QSERDES_V5_COM_CP_CTRL_MODE1			0x078

#define QSERDES_V5_COM_PLL_RCTRL_MODE0			0x07c

#define QSERDES_V5_COM_PLL_RCTRL_MODE1			0x080

#define QSERDES_V5_COM_PLL_CCTRL_MODE0			0x084

#define QSERDES_V5_COM_PLL_CCTRL_MODE1			0x088

#define QSERDES_V5_COM_SYSCLK_EN_SEL			0x094

#define QSERDES_V5_COM_LOCK_CMP_EN			0x0a4

#define QSERDES_V5_COM_LOCK_CMP_CFG			0x0a8

#define QSERDES_V5_COM_LOCK_CMP1_MODE0			0x0ac

#define QSERDES_V5_COM_LOCK_CMP2_MODE0			0x0b0

#define QSERDES_V5_COM_LOCK_CMP1_MODE1			0x0b4

#define QSERDES_V5_COM_LOCK_CMP2_MODE1			0x0b8

#define QSERDES_V5_COM_DEC_START_MODE0			0x0bc

#define QSERDES_V5_COM_DEC_START_MODE1			0x0c4

#define QSERDES_V5_COM_DIV_FRAC_START1_MODE0		0x0cc

#define QSERDES_V5_COM_DIV_FRAC_START2_MODE0		0x0d0

#define QSERDES_V5_COM_DIV_FRAC_START3_MODE0		0x0d4

#define QSERDES_V5_COM_DIV_FRAC_START1_MODE1		0x0d8

#define QSERDES_V5_COM_DIV_FRAC_START2_MODE1		0x0dc

#define QSERDES_V5_COM_DIV_FRAC_START3_MODE1		0x0e0

#define QSERDES_V5_COM_VCO_TUNE_MAP			0x10c

#define QSERDES_V5_COM_VCO_TUNE1_MODE0			0x110

#define QSERDES_V5_COM_VCO_TUNE2_MODE0			0x114

#define QSERDES_V5_COM_VCO_TUNE1_MODE1			0x118

#define QSERDES_V5_COM_VCO_TUNE2_MODE1			0x11c

#define QSERDES_V5_COM_VCO_TUNE_INITVAL2		0x124

#define QSERDES_V5_COM_CLK_SELECT			0x154

#define QSERDES_V5_COM_HSCLK_SEL			0x158

#define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL		0x15c

#define QSERDES_V5_COM_CORECLK_DIV_MODE0		0x168

#define QSERDES_V5_COM_CORECLK_DIV_MODE1		0x16c

#define QSERDES_V5_COM_CORE_CLK_EN			0x174

#define QSERDES_V5_COM_CMN_CONFIG			0x17c

#define QSERDES_V5_COM_CMN_MISC1			0x19c

#define QSERDES_V5_COM_CMN_MODE				0x1a0

#define QSERDES_V5_COM_CMN_MODE_CONTD			0x1a4

#define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL		0x1a8

#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0	0x1ac

#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0	0x1b0

#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1	0x1b4

#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1	0x1b8

#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL		0x1bc



#endif

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h

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/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (c) 2017, The Linux Foundation. All rights reserved.

 */



#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_H_

#define QCOM_PHY_QMP_QSERDES_TXRX_V5_H_



/* Only for QMP V5 PHY - TX registers */

#define QSERDES_V5_TX_RES_CODE_LANE_TX			0x034

#define QSERDES_V5_TX_RES_CODE_LANE_RX			0x038

#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX		0x03c

#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX		0x040

#define QSERDES_V5_TX_LANE_MODE_1			0x084

#define QSERDES_V5_TX_LANE_MODE_2			0x088

#define QSERDES_V5_TX_LANE_MODE_3			0x08c

#define QSERDES_V5_TX_LANE_MODE_4			0x090

#define QSERDES_V5_TX_LANE_MODE_5			0x094

#define QSERDES_V5_TX_RCV_DETECT_LVL_2			0x0a4

#define QSERDES_V5_TX_TRAN_DRVR_EMP_EN			0x0c0

#define QSERDES_V5_TX_PI_QEC_CTRL			0x0e4

#define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1	0x178

#define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1	0x17c

#define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1	0x180

#define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1	0x184



/* Only for QMP V5 PHY - RX registers */

#define QSERDES_V5_RX_UCDR_FO_GAIN			0x008

#define QSERDES_V5_RX_UCDR_SO_GAIN			0x014

#define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN		0x030

#define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE	0x034

#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW		0x03c

#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH		0x040

#define QSERDES_V5_RX_UCDR_PI_CONTROLS			0x044

#define QSERDES_V5_RX_UCDR_PI_CTRL2			0x048

#define QSERDES_V5_RX_UCDR_SB2_THRESH1			0x04c

#define QSERDES_V5_RX_UCDR_SB2_THRESH2			0x050

#define QSERDES_V5_RX_UCDR_SB2_GAIN1			0x054

#define QSERDES_V5_RX_UCDR_SB2_GAIN2			0x058

#define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE		0x060

#define QSERDES_V5_RX_RCLK_AUXDATA_SEL			0x064

#define QSERDES_V5_RX_AC_JTAG_ENABLE			0x068

#define QSERDES_V5_RX_AC_JTAG_MODE			0x078

#define QSERDES_V5_RX_RX_TERM_BW			0x080

#define QSERDES_V5_RX_TX_ADAPT_POST_THRESH		0x0cc

#define QSERDES_V5_RX_VGA_CAL_CNTRL1			0x0d4

#define QSERDES_V5_RX_VGA_CAL_CNTRL2			0x0d8

#define QSERDES_V5_RX_GM_CAL				0x0dc

#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1		0x0e8

#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2		0x0ec

#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3		0x0f0

#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4		0x0f4

#define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW		0x0f8

#define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH		0x0fc

#define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME		0x100

#define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1	0x110

#define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2		0x114

#define QSERDES_V5_RX_SIGDET_ENABLES			0x118

#define QSERDES_V5_RX_SIGDET_CNTRL			0x11c

#define QSERDES_V5_RX_SIGDET_LVL			0x120

#define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL		0x124

#define QSERDES_V5_RX_RX_BAND				0x128

#define QSERDES_V5_RX_RX_MODE_00_LOW			0x15c

#define QSERDES_V5_RX_RX_MODE_00_HIGH			0x160

#define QSERDES_V5_RX_RX_MODE_00_HIGH2			0x164

#define QSERDES_V5_RX_RX_MODE_00_HIGH3			0x168

#define QSERDES_V5_RX_RX_MODE_00_HIGH4			0x16c

#define QSERDES_V5_RX_RX_MODE_01_LOW			0x170

#define QSERDES_V5_RX_RX_MODE_01_HIGH			0x174

#define QSERDES_V5_RX_RX_MODE_01_HIGH2			0x178

#define QSERDES_V5_RX_RX_MODE_01_HIGH3			0x17c

#define QSERDES_V5_RX_RX_MODE_01_HIGH4			0x180

#define QSERDES_V5_RX_RX_MODE_10_LOW			0x184

#define QSERDES_V5_RX_RX_MODE_10_HIGH			0x188

#define QSERDES_V5_RX_RX_MODE_10_HIGH2			0x18c

#define QSERDES_V5_RX_RX_MODE_10_HIGH3			0x190

#define QSERDES_V5_RX_RX_MODE_10_HIGH4			0x194

#define QSERDES_V5_RX_DFE_EN_TIMER			0x1a0

#define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET		0x1a4

#define QSERDES_V5_RX_DCC_CTRL1				0x1a8

#define QSERDES_V5_RX_VTH_CODE				0x1b0



#endif

drivers/phy/qualcomm/phy-qcom-qmp.h

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@@ -15,6 +15,9 @@ 
#include "phy-qcom-qmp-qserdes-com-v4.h"

#include "phy-qcom-qmp-qserdes-txrx-v4.h"



#include "phy-qcom-qmp-qserdes-com-v5.h"

#include "phy-qcom-qmp-qserdes-txrx-v5.h"



/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */



#define QSERDES_PLL_BG_TIMER				0x00c
@@ -612,142 +615,12 @@ 
#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2		0x824

#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2		0x828



/* Only for QMP V5 PHY - QSERDES COM registers */

#define QSERDES_V5_COM_SSC_EN_CENTER			0x010

#define QSERDES_V5_COM_SSC_PER1				0x01c

#define QSERDES_V5_COM_SSC_PER2				0x020

#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0		0x024

#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0		0x028

#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1		0x030

#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1		0x034

#define QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN		0x044

#define QSERDES_V5_COM_CLK_ENABLE1			0x048

#define QSERDES_V5_COM_SYSCLK_BUF_ENABLE		0x050

#define QSERDES_V5_COM_PLL_IVCO				0x058

#define QSERDES_V5_COM_CP_CTRL_MODE0			0x074

#define QSERDES_V5_COM_CP_CTRL_MODE1			0x078

#define QSERDES_V5_COM_PLL_RCTRL_MODE0			0x07c

#define QSERDES_V5_COM_PLL_RCTRL_MODE1			0x080

#define QSERDES_V5_COM_PLL_CCTRL_MODE0			0x084

#define QSERDES_V5_COM_PLL_CCTRL_MODE1			0x088

#define QSERDES_V5_COM_SYSCLK_EN_SEL			0x094

#define QSERDES_V5_COM_LOCK_CMP_EN			0x0a4

#define QSERDES_V5_COM_LOCK_CMP_CFG			0x0a8

#define QSERDES_V5_COM_LOCK_CMP1_MODE0			0x0ac

#define QSERDES_V5_COM_LOCK_CMP2_MODE0			0x0b0

#define QSERDES_V5_COM_LOCK_CMP1_MODE1			0x0b4

#define QSERDES_V5_COM_LOCK_CMP2_MODE1			0x0b8

#define QSERDES_V5_COM_DEC_START_MODE0			0x0bc

#define QSERDES_V5_COM_DEC_START_MODE1			0x0c4

#define QSERDES_V5_COM_DIV_FRAC_START1_MODE0		0x0cc

#define QSERDES_V5_COM_DIV_FRAC_START2_MODE0		0x0d0

#define QSERDES_V5_COM_DIV_FRAC_START3_MODE0		0x0d4

#define QSERDES_V5_COM_DIV_FRAC_START1_MODE1		0x0d8

#define QSERDES_V5_COM_DIV_FRAC_START2_MODE1		0x0dc

#define QSERDES_V5_COM_DIV_FRAC_START3_MODE1		0x0e0

#define QSERDES_V5_COM_VCO_TUNE_MAP			0x10c

#define QSERDES_V5_COM_VCO_TUNE1_MODE0			0x110

#define QSERDES_V5_COM_VCO_TUNE2_MODE0			0x114

#define QSERDES_V5_COM_VCO_TUNE1_MODE1			0x118

#define QSERDES_V5_COM_VCO_TUNE2_MODE1			0x11c

#define QSERDES_V5_COM_VCO_TUNE_INITVAL2		0x124

#define QSERDES_V5_COM_CLK_SELECT			0x154

#define QSERDES_V5_COM_HSCLK_SEL			0x158

#define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL		0x15c

#define QSERDES_V5_COM_CORECLK_DIV_MODE0		0x168

#define QSERDES_V5_COM_CORECLK_DIV_MODE1		0x16c

#define QSERDES_V5_COM_CORE_CLK_EN			0x174

#define QSERDES_V5_COM_CMN_CONFIG			0x17c

#define QSERDES_V5_COM_CMN_MISC1			0x19c

#define QSERDES_V5_COM_CMN_MODE				0x1a0

#define QSERDES_V5_COM_CMN_MODE_CONTD			0x1a4

#define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL		0x1a8

#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0	0x1ac

#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0	0x1b0

#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1	0x1b4

#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1	0x1b8

#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL		0x1bc



/* Only for QMP V5 PHY - TX registers */

#define QSERDES_V5_TX_RES_CODE_LANE_TX			0x34

#define QSERDES_V5_TX_RES_CODE_LANE_RX			0x38

#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX		0x3c

#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX		0x40

#define QSERDES_V5_TX_LANE_MODE_1			0x84

#define QSERDES_V5_TX_LANE_MODE_2			0x88

#define QSERDES_V5_TX_LANE_MODE_3			0x8c

#define QSERDES_V5_TX_LANE_MODE_4			0x90

#define QSERDES_V5_TX_LANE_MODE_5			0x94

#define QSERDES_V5_TX_RCV_DETECT_LVL_2			0xa4

#define QSERDES_V5_TX_TRAN_DRVR_EMP_EN			0xc0

#define QSERDES_V5_TX_PI_QEC_CTRL			0xe4

#define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1	0x178

#define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1	0x17c

#define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1	0x180

#define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1	0x184



/* Only for QMP V5_20 PHY - TX registers */

#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX	0x30

#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX	0x34

#define QSERDES_V5_20_TX_LANE_MODE_1			0x78

#define QSERDES_V5_20_TX_LANE_MODE_2			0x7c



/* Only for QMP V5 PHY - RX registers */

#define QSERDES_V5_RX_UCDR_FO_GAIN			0x008

#define QSERDES_V5_RX_UCDR_SO_GAIN			0x014

#define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN		0x030

#define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE	0x034

#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW		0x03c

#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH		0x040

#define QSERDES_V5_RX_UCDR_PI_CONTROLS			0x044

#define QSERDES_V5_RX_UCDR_PI_CTRL2			0x048

#define QSERDES_V5_RX_UCDR_SB2_THRESH1			0x04c

#define QSERDES_V5_RX_UCDR_SB2_THRESH2			0x050

#define QSERDES_V5_RX_UCDR_SB2_GAIN1			0x054

#define QSERDES_V5_RX_UCDR_SB2_GAIN2			0x058

#define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE		0x060

#define QSERDES_V5_RX_RCLK_AUXDATA_SEL			0x064

#define QSERDES_V5_RX_AC_JTAG_ENABLE			0x068

#define QSERDES_V5_RX_AC_JTAG_MODE			0x078

#define QSERDES_V5_RX_RX_TERM_BW			0x080

#define QSERDES_V5_RX_TX_ADAPT_POST_THRESH		0x0cc

#define QSERDES_V5_RX_VGA_CAL_CNTRL1			0x0d4

#define QSERDES_V5_RX_VGA_CAL_CNTRL2			0x0d8

#define QSERDES_V5_RX_GM_CAL				0x0dc

#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1		0x0e8

#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2		0x0ec

#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3		0x0f0

#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4		0x0f4

#define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW		0x0f8

#define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH		0x0fc

#define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME		0x100

#define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1	0x110

#define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2		0x114

#define QSERDES_V5_RX_SIGDET_ENABLES			0x118

#define QSERDES_V5_RX_SIGDET_CNTRL			0x11c

#define QSERDES_V5_RX_SIGDET_LVL			0x120

#define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL		0x124

#define QSERDES_V5_RX_RX_BAND				0x128

#define QSERDES_V5_RX_RX_MODE_00_LOW			0x15c

#define QSERDES_V5_RX_RX_MODE_00_HIGH			0x160

#define QSERDES_V5_RX_RX_MODE_00_HIGH2			0x164

#define QSERDES_V5_RX_RX_MODE_00_HIGH3			0x168

#define QSERDES_V5_RX_RX_MODE_00_HIGH4			0x16c

#define QSERDES_V5_RX_RX_MODE_01_LOW			0x170

#define QSERDES_V5_RX_RX_MODE_01_HIGH			0x174

#define QSERDES_V5_RX_RX_MODE_01_HIGH2			0x178

#define QSERDES_V5_RX_RX_MODE_01_HIGH3			0x17c

#define QSERDES_V5_RX_RX_MODE_01_HIGH4			0x180

#define QSERDES_V5_RX_RX_MODE_10_LOW			0x184

#define QSERDES_V5_RX_RX_MODE_10_HIGH			0x188

#define QSERDES_V5_RX_RX_MODE_10_HIGH2			0x18c

#define QSERDES_V5_RX_RX_MODE_10_HIGH3			0x190

#define QSERDES_V5_RX_RX_MODE_10_HIGH4			0x194

#define QSERDES_V5_RX_DFE_EN_TIMER			0x1a0

#define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET		0x1a4

#define QSERDES_V5_RX_DCC_CTRL1				0x1a8

#define QSERDES_V5_RX_VTH_CODE				0x1b0



/* Only for QMP V5_20 PHY - RX registers */

#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2		0x008

#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3		0x00c