Commit f23ba46e authored by Icenowy Zheng's avatar Icenowy Zheng Committed by Jernej Skrabec
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ARM: dts: suniv: add USB-related device nodes 



The suniv SoC has a USB OTG controller and a USB PHY like other
Allwinner SoCs.

Add their device tree node.

Signed-off-by: default avatarIcenowy Zheng <uwu@icenowy.me>
Reviewed-by: default avatarAndre Przywara <andre.przywara@arm.com>
Acked-by: default avatarJernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/20230319212936.26649-2-andre.przywara@arm.com


Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@gmail.com>
parent fce449f5

arch/arm/boot/dts/suniv-f1c100s.dtsi

+26 −0
Original line number Diff line number Diff line
@@ -133,6 +133,32 @@ mmc1: mmc@1c10000 { 
			#size-cells = <0>;

		};



		usb_otg: usb@1c13000 {

			compatible = "allwinner,suniv-f1c100s-musb";

			reg = <0x01c13000 0x0400>;

			clocks = <&ccu CLK_BUS_OTG>;

			resets = <&ccu RST_BUS_OTG>;

			interrupts = <26>;

			interrupt-names = "mc";

			phys = <&usbphy 0>;

			phy-names = "usb";

			extcon = <&usbphy 0>;

			allwinner,sram = <&otg_sram 1>;

			status = "disabled";

		};



		usbphy: phy@1c13400 {

			compatible = "allwinner,suniv-f1c100s-usb-phy";

			reg = <0x01c13400 0x10>;

			reg-names = "phy_ctrl";

			clocks = <&ccu CLK_USB_PHY0>;

			clock-names = "usb0_phy";

			resets = <&ccu RST_USB_PHY0>;

			reset-names = "usb0_reset";

			#phy-cells = <1>;

			status = "disabled";

		};



		ccu: clock@1c20000 {

			compatible = "allwinner,suniv-f1c100s-ccu";

			reg = <0x01c20000 0x400>;