Commit f2803ee9 authored by Vinod Koul's avatar Vinod Koul Committed by Dmitry Baryshkov
Browse files

drm/msm/disp/dpu1: Add DSC support in RM 



This add the bits in RM to enable the DSC blocks

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
Patchwork: https://patchwork.freedesktop.org/patch/480928/
Link: https://lore.kernel.org/r/20220406094031.1027376-12-vkoul@kernel.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 7e9cc175

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h

+1 −0
Original line number Diff line number Diff line
@@ -145,6 +145,7 @@ struct dpu_global_state { 
	uint32_t mixer_to_enc_id[LM_MAX - LM_0];

	uint32_t ctl_to_enc_id[CTL_MAX - CTL_0];

	uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0];

	uint32_t dsc_to_enc_id[DSC_MAX - DSC_0];

};



struct dpu_global_state

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c

+56 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#include "dpu_hw_intf.h"

#include "dpu_hw_dspp.h"

#include "dpu_hw_merge3d.h"

#include "dpu_hw_dsc.h"

#include "dpu_encoder.h"

#include "dpu_trace.h"
@@ -77,6 +78,15 @@ int dpu_rm_destroy(struct dpu_rm *rm) 
	for (i = 0; i < ARRAY_SIZE(rm->hw_intf); i++)

		dpu_hw_intf_destroy(rm->hw_intf[i]);



	for (i = 0; i < ARRAY_SIZE(rm->dsc_blks); i++) {

		struct dpu_hw_dsc *hw;



		if (rm->dsc_blks[i]) {

			hw = to_dpu_hw_dsc(rm->dsc_blks[i]);

			dpu_hw_dsc_destroy(hw);

		}

	}



	return 0;

}
@@ -210,6 +220,19 @@ int dpu_rm_init(struct dpu_rm *rm, 
		rm->dspp_blks[dspp->id - DSPP_0] = &hw->base;

	}



	for (i = 0; i < cat->dsc_count; i++) {

		struct dpu_hw_dsc *hw;

		const struct dpu_dsc_cfg *dsc = &cat->dsc[i];



		hw = dpu_hw_dsc_init(dsc->id, mmio, cat);

		if (IS_ERR_OR_NULL(hw)) {

			rc = PTR_ERR(hw);

			DPU_ERROR("failed dsc object creation: err %d\n", rc);

			goto fail;

		}

		rm->dsc_blks[dsc->id - DSC_0] = &hw->base;

	}



	return 0;



fail:
@@ -441,6 +464,28 @@ static int _dpu_rm_reserve_ctls( 
	return 0;

}



static int _dpu_rm_reserve_dsc(struct dpu_rm *rm,

			       struct dpu_global_state *global_state,

			       struct drm_encoder *enc,

			       const struct msm_display_topology *top)

{

	int num_dsc = top->num_dsc;

	int i;



	/* check if DSC required are allocated or not */

	for (i = 0; i < num_dsc; i++) {

		if (global_state->dsc_to_enc_id[i]) {

			DPU_ERROR("DSC %d is already allocated\n", i);

			return -EIO;

		}

	}



	for (i = 0; i < num_dsc; i++)

		global_state->dsc_to_enc_id[i] = enc->base.id;



	return 0;

}



static int _dpu_rm_make_reservation(

		struct dpu_rm *rm,

		struct dpu_global_state *global_state,
@@ -462,6 +507,10 @@ static int _dpu_rm_make_reservation( 
		return ret;

	}



	ret  = _dpu_rm_reserve_dsc(rm, global_state, enc, &reqs->topology);

	if (ret)

		return ret;



	return ret;

}
@@ -499,6 +548,8 @@ void dpu_rm_release(struct dpu_global_state *global_state, 
		ARRAY_SIZE(global_state->mixer_to_enc_id), enc->base.id);

	_dpu_rm_clear_mapping(global_state->ctl_to_enc_id,

		ARRAY_SIZE(global_state->ctl_to_enc_id), enc->base.id);

	_dpu_rm_clear_mapping(global_state->dsc_to_enc_id,

		ARRAY_SIZE(global_state->dsc_to_enc_id), enc->base.id);

}



int dpu_rm_reserve(
@@ -567,6 +618,11 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, 
		hw_to_enc_id = global_state->dspp_to_enc_id;

		max_blks = ARRAY_SIZE(rm->dspp_blks);

		break;

	case DPU_HW_BLK_DSC:

		hw_blks = rm->dsc_blks;

		hw_to_enc_id = global_state->dsc_to_enc_id;

		max_blks = ARRAY_SIZE(rm->dsc_blks);

		break;

	default:

		DPU_ERROR("blk type %d not managed by rm\n", type);

		return 0;

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h

+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ struct dpu_rm { 
	struct dpu_hw_intf *hw_intf[INTF_MAX - INTF_0];

	struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];

	struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];

	struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];

};



/**