Commit f3a8a46d authored by Yong Wu's avatar Yong Wu Committed by Will Deacon
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iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek 



The standard input iova bits is 32. MediaTek quad the lvl1 pagetable
(4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach
34bit.

Signed-off-by: default avatarYong Wu <yong.wu@mediatek.com>
Reviewed-by: default avatarRobin Murphy <robin.murphy@arm.com>
Reviewed-by: default avatarTomasz Figa <tfiga@chromium.org>
Link: https://lore.kernel.org/r/20210111111914.22211-14-yong.wu@mediatek.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 468ea0bf

drivers/iommu/io-pgtable-arm-v7s.c

+4 −3
Original line number Diff line number Diff line
@@ -45,9 +45,10 @@ 
/*

 * We have 32 bits total; 12 bits resolved at level 1, 8 bits at level 2,

 * and 12 bits in a page.

 * MediaTek extend 2 bits to reach 34bits, 14 bits at lvl1 and 8 bits at lvl2.

 */

#define ARM_V7S_ADDR_BITS		32

#define _ARM_V7S_LVL_BITS(lvl, cfg)	((lvl) == 1 ? 12 : 8)

#define _ARM_V7S_LVL_BITS(lvl, cfg)	((lvl) == 1 ? ((cfg)->ias - 20) : 8)

#define ARM_V7S_LVL_SHIFT(lvl)		((lvl) == 1 ? 20 : 12)

#define ARM_V7S_TABLE_SHIFT		10
@@ -61,7 +62,7 @@ 
#define _ARM_V7S_IDX_MASK(lvl, cfg)	(ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1)

#define ARM_V7S_LVL_IDX(addr, lvl, cfg)	({				\

	int _l = lvl;							\

	((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \

	((addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \

})



/*
@@ -748,7 +749,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, 
{

	struct arm_v7s_io_pgtable *data;



	if (cfg->ias > ARM_V7S_ADDR_BITS)

	if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))

		return NULL;



	if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS))