Commit f400b6ce authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/pm: rework i2c xfers on arcturus (v5)



Make it generic so we can support more than just EEPROMs.

v2: fix restart handling between transactions.
v3: handle 7 to 8 bit addr conversion
v4: Fix &req --> req. (Luben T)
v5: squash in i2c channel fix

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarLuben Tuikov <luben.tuikov@amd.com>
Reviewed-by: default avatarLuben Tuikov <luben.tuikov@amd.com>
parent 5125c96a
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+58 −171
Original line number Diff line number Diff line
@@ -1936,197 +1936,84 @@ static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
	return ret;
}

static void arcturus_fill_i2c_req(SwI2cRequest_t  *req, bool write,
				  uint8_t address, uint32_t numbytes,
				  uint8_t *data)
{
	int i;

	req->I2CcontrollerPort = 0;
	req->I2CSpeed = 2;
	req->SlaveAddress = address;
	req->NumCmds = numbytes;

	for (i = 0; i < numbytes; i++) {
		SwI2cCmd_t *cmd =  &req->SwI2cCmds[i];

		/* First 2 bytes are always write for lower 2b EEPROM address */
		if (i < 2)
			cmd->Cmd = 1;
		else
			cmd->Cmd = write;


		/* Add RESTART for read  after address filled */
		cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;

		/* Add STOP in the end */
		cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;

		/* Fill with data regardless if read or write to simplify code */
		cmd->RegisterAddr = data[i];
	}
}

static int arcturus_i2c_read_data(struct i2c_adapter *control,
					       uint8_t address,
					       uint8_t *data,
					       uint32_t numbytes)
static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap,
			     struct i2c_msg *msgs, int num)
{
	uint32_t  i, ret = 0;
	SwI2cRequest_t req;
	struct amdgpu_device *adev = to_amdgpu_device(control);
	struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
	struct smu_table_context *smu_table = &adev->smu.smu_table;
	struct smu_table *table = &smu_table->driver_table;

	if (numbytes > MAX_SW_I2C_COMMANDS) {
		dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
			numbytes, MAX_SW_I2C_COMMANDS);
	SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
	u16 bytes_to_transfer, remaining_bytes, msg_bytes;
	u16 available_bytes = MAX_SW_I2C_COMMANDS;
	int i, j, r, c;
	u8 slave;

	/* only support a single slave addr per transaction */
	slave = msgs[0].addr;
	for (i = 0; i < num; i++) {
		if (slave != msgs[i].addr)
			return -EINVAL;
		bytes_to_transfer += min(msgs[i].len, available_bytes);
		available_bytes -= bytes_to_transfer;
	}

	memset(&req, 0, sizeof(req));
	arcturus_fill_i2c_req(&req, false, address, numbytes, data);

	mutex_lock(&adev->smu.mutex);
	/* Now read data starting with that address */
	ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
					true);
	mutex_unlock(&adev->smu.mutex);

	if (!ret) {
		SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
	req = kzalloc(sizeof(*req), GFP_KERNEL);
	if (!req)
		return -ENOMEM;

		/* Assume SMU  fills res.SwI2cCmds[i].Data with read bytes */
		for (i = 0; i < numbytes; i++)
			data[i] = res->SwI2cCmds[i].Data;
	req->I2CcontrollerPort = 0;
	req->I2CSpeed = I2C_SPEED_FAST_400K;
	req->SlaveAddress = slave << 1; /* 8 bit addresses */
	req->NumCmds = bytes_to_transfer;

		dev_dbg(adev->dev, "arcturus_i2c_read_data, address = %x, bytes = %d, data :",
				  (uint16_t)address, numbytes);
	remaining_bytes = bytes_to_transfer;
	c = 0;
	for (i = 0; i < num; i++) {
		struct i2c_msg *msg = &msgs[i];

		print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
			       8, 1, data, numbytes, false);
	} else
		dev_err(adev->dev, "arcturus_i2c_read_data - error occurred :%x", ret);
		msg_bytes = min(msg->len, remaining_bytes);
		for (j = 0; j < msg_bytes; j++) {
			SwI2cCmd_t *cmd = &req->SwI2cCmds[c++];

	return ret;
			remaining_bytes--;
			if (!(msg[i].flags & I2C_M_RD)) {
				/* write */
				cmd->CmdConfig |= I2C_CMD_WRITE;
				cmd->RegisterAddr = msg->buf[j];
			}
			if ((msg[i].flags & I2C_M_STOP) ||
			    (!remaining_bytes))
				cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
			if ((i > 0) && !(msg[i].flags & I2C_M_NOSTART))
				cmd->CmdConfig |= CMDCONFIG_RESTART_BIT;
		}

static int arcturus_i2c_write_data(struct i2c_adapter *control,
						uint8_t address,
						uint8_t *data,
						uint32_t numbytes)
{
	uint32_t ret;
	SwI2cRequest_t req;
	struct amdgpu_device *adev = to_amdgpu_device(control);

	if (numbytes > MAX_SW_I2C_COMMANDS) {
		dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
			numbytes, MAX_SW_I2C_COMMANDS);
		return -EINVAL;
	}

	memset(&req, 0, sizeof(req));
	arcturus_fill_i2c_req(&req, true, address, numbytes, data);

	mutex_lock(&adev->smu.mutex);
	ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
	r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
	mutex_unlock(&adev->smu.mutex);

	if (!ret) {
		dev_dbg(adev->dev, "arcturus_i2c_write(), address = %x, bytes = %d , data: ",
					 (uint16_t)address, numbytes);

		print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
			       8, 1, data, numbytes, false);
		/*
		 * According to EEPROM spec there is a MAX of 10 ms required for
		 * EEPROM to flush internal RX buffer after STOP was issued at the
		 * end of write transaction. During this time the EEPROM will not be
		 * responsive to any more commands - so wait a bit more.
		 */
		msleep(10);

	} else
		dev_err(adev->dev, "arcturus_i2c_write- error occurred :%x", ret);

	return ret;
}

static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap,
			      struct i2c_msg *msgs, int num)
{
	uint32_t  i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
	uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };

	for (i = 0; i < num; i++) {
		/*
		 * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
		 * once and hence the data needs to be spliced into chunks and sent each
		 * chunk separately
		 */
		data_size = msgs[i].len - 2;
		data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
		next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
		data_ptr = msgs[i].buf + 2;

		for (j = 0; j < data_size / data_chunk_size; j++) {
			/* Insert the EEPROM dest addess, bits 0-15 */
			data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
			data_chunk[1] = (next_eeprom_addr & 0xff);

			if (msgs[i].flags & I2C_M_RD) {
				ret = arcturus_i2c_read_data(i2c_adap,
							     (uint8_t)msgs[i].addr,
							     data_chunk, MAX_SW_I2C_COMMANDS);

				memcpy(data_ptr, data_chunk + 2, data_chunk_size);
			} else {

				memcpy(data_chunk + 2, data_ptr, data_chunk_size);

				ret = arcturus_i2c_write_data(i2c_adap,
							      (uint8_t)msgs[i].addr,
							      data_chunk, MAX_SW_I2C_COMMANDS);
			}

			if (ret) {
				num = -EIO;
	if (r)
		goto fail;
			}

			next_eeprom_addr += data_chunk_size;
			data_ptr += data_chunk_size;
		}

		if (data_size % data_chunk_size) {
			data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
			data_chunk[1] = (next_eeprom_addr & 0xff);

			if (msgs[i].flags & I2C_M_RD) {
				ret = arcturus_i2c_read_data(i2c_adap,
							     (uint8_t)msgs[i].addr,
							     data_chunk, (data_size % data_chunk_size) + 2);

				memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
			} else {
				memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
	remaining_bytes = bytes_to_transfer;
	c = 0;
	for (i = 0; i < num; i++) {
		struct i2c_msg *msg = &msgs[i];

				ret = arcturus_i2c_write_data(i2c_adap,
							      (uint8_t)msgs[i].addr,
							      data_chunk, (data_size % data_chunk_size) + 2);
			}
		msg_bytes = min(msg->len, remaining_bytes);
		for (j = 0; j < msg_bytes; j++) {
			SwI2cCmd_t *cmd = &res->SwI2cCmds[c++];

			if (ret) {
				num = -EIO;
				goto fail;
			}
			remaining_bytes--;
			if (msg[i].flags & I2C_M_RD)
				msg->buf[j] = cmd->Data;
		}
	}
	r = bytes_to_transfer;

fail:
	return num;
	kfree(req);

	return r;
}

static u32 arcturus_i2c_func(struct i2c_adapter *adap)