Commit f458b770 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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arm64: dts: renesas: r9a07g054: Fillup the OSTM{0,1,2} stub nodes 



Fillup the OSTM{0,1,2} stub nodes in RZ/V2L (R9A07G054) SoC DTSI.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220227203744.18355-8-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 8d3da65c

arch/arm64/boot/dts/renesas/r9a07g054.dtsi

+21 −3
Original line number Diff line number Diff line
@@ -629,18 +629,36 @@ wdt2: watchdog@12800400 { 
		};



		ostm0: timer@12801000 {

			compatible = "renesas,r9a07g054-ostm",

				     "renesas,ostm";

			reg = <0x0 0x12801000 0x0 0x400>;

			/* place holder */

			interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;

			clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>;

			resets = <&cpg R9A07G054_OSTM0_PRESETZ>;

			power-domains = <&cpg>;

			status = "disabled";

		};



		ostm1: timer@12801400 {

			compatible = "renesas,r9a07g054-ostm",

				     "renesas,ostm";

			reg = <0x0 0x12801400 0x0 0x400>;

			/* place holder */

			interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;

			clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>;

			resets = <&cpg R9A07G054_OSTM1_PRESETZ>;

			power-domains = <&cpg>;

			status = "disabled";

		};



		ostm2: timer@12801800 {

			compatible = "renesas,r9a07g054-ostm",

				     "renesas,ostm";

			reg = <0x0 0x12801800 0x0 0x400>;

			/* place holder */

			interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;

			clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>;

			resets = <&cpg R9A07G054_OSTM2_PRESETZ>;

			power-domains = <&cpg>;

			status = "disabled";

		};

	};