Commit f5d83b71 authored by William Zhang's avatar William Zhang Committed by Florian Fainelli
Browse files

arm64: dts: broadcom: bcmbca: Add spi controller node 



Add support for HSSPI controller in ARMv8 chip dts files.

Signed-off-by: default avatarWilliam Zhang <william.zhang@broadcom.com>
Link: https://lore.kernel.org/r/20230207065826.285013-5-william.zhang@broadcom.com


Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
parent 47600f84

arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi

+18 −0
Original line number Diff line number Diff line
@@ -107,6 +107,12 @@ periph_clk: periph_clk { 
			clock-frequency = <50000000>;

			clock-output-names = "periph";

		};



		hsspi_pll: hsspi-pll {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <400000000>;

		};

	};



	soc {
@@ -531,6 +537,18 @@ leds: leds@800 { 
			#size-cells = <0>;

		};



		hsspi: spi@1000{

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "brcm,bcm4908-hsspi", "brcm,bcmbca-hsspi-v1.0";

			reg = <0x1000 0x600>;

			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&hsspi_pll &hsspi_pll>;

			clock-names = "hsspi", "pll";

			num-cs = <8>;

			status = "disabled";

		};



		nand-controller@1800 {

			#address-cells = <1>;

			#size-cells = <0>;

arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -79,6 +79,7 @@ periph_clk: periph-clk { 
			#clock-cells = <0>;

			clock-frequency = <200000000>;

		};



		uart_clk: uart-clk {

			compatible = "fixed-factor-clock";

			#clock-cells = <0>;
@@ -86,6 +87,12 @@ uart_clk: uart-clk { 
			clock-div = <4>;

			clock-mult = <1>;

		};



		hsspi_pll: hsspi-pll {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <200000000>;

		};

	};



	psci {
@@ -117,6 +124,19 @@ bus@ff800000 { 
		#size-cells = <1>;

		ranges = <0x0 0x0 0xff800000 0x800000>;



		hsspi: spi@1000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "brcm,bcm4912-hsspi", "brcm,bcmbca-hsspi-v1.1";

			reg = <0x1000 0x600>, <0x2610 0x4>;

			reg-names = "hsspi", "spim-ctrl";

			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&hsspi_pll &hsspi_pll>;

			clock-names = "hsspi", "pll";

			num-cs = <8>;

			status = "disabled";

		};



		uart0: serial@12000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0x12000 0x1000>;

arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi

+19 −0
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@ periph_clk: periph-clk { 
			#clock-cells = <0>;

			clock-frequency = <200000000>;

		};



		uart_clk: uart-clk {

			compatible = "fixed-factor-clock";

			#clock-cells = <0>;
@@ -67,6 +68,12 @@ uart_clk: uart-clk { 
			clock-div = <4>;

			clock-mult = <1>;

		};



		hsspi_pll: hsspi-pll {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <200000000>;

		};

	};



	psci {
@@ -99,6 +106,18 @@ bus@ff800000 { 
		#size-cells = <1>;

		ranges = <0x0 0x0 0xff800000 0x800000>;



		hsspi: spi@1000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "brcm,bcm63146-hsspi", "brcm,bcmbca-hsspi-v1.0";

			reg = <0x1000 0x600>;

			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&hsspi_pll &hsspi_pll>;

			clock-names = "hsspi", "pll";

			num-cs = <8>;

			status = "disabled";

		};



		uart0: serial@12000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0x12000 0x1000>;

arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi

+19 −0
Original line number Diff line number Diff line
@@ -79,6 +79,7 @@ periph_clk: periph-clk { 
			#clock-cells = <0>;

			clock-frequency = <200000000>;

		};



		uart_clk: uart-clk {

			compatible = "fixed-factor-clock";

			#clock-cells = <0>;
@@ -86,6 +87,12 @@ uart_clk: uart-clk { 
			clock-div = <4>;

			clock-mult = <1>;

		};



		hsspi_pll: hsspi-pll {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <400000000>;

		};

	};



	psci {
@@ -117,6 +124,18 @@ bus@ff800000 { 
		#size-cells = <1>;

		ranges = <0x0 0x0 0xff800000 0x800000>;



		hsspi: spi@1000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "brcm,bcm63158-hsspi", "brcm,bcmbca-hsspi-v1.0";

			reg = <0x1000 0x600>;

			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&hsspi_pll &hsspi_pll>;

			clock-names = "hsspi", "pll";

			num-cs = <8>;

			status = "disabled";

		};



		uart0: serial@12000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0x12000 0x1000>;

arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -79,6 +79,7 @@ periph_clk: periph-clk { 
			#clock-cells = <0>;

			clock-frequency = <200000000>;

		};



		uart_clk: uart-clk {

			compatible = "fixed-factor-clock";

			#clock-cells = <0>;
@@ -86,6 +87,12 @@ uart_clk: uart-clk { 
			clock-div = <4>;

			clock-mult = <1>;

		};



		hsspi_pll: hsspi-pll {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <200000000>;

		};

	};



	psci {
@@ -117,6 +124,19 @@ bus@ff800000 { 
		#size-cells = <1>;

		ranges = <0x0 0x0 0xff800000 0x800000>;



		hsspi: spi@1000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "brcm,bcm6813-hsspi", "brcm,bcmbca-hsspi-v1.1";

			reg = <0x1000 0x600>, <0x2610 0x4>;

			reg-names = "hsspi", "spim-ctrl";

			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&hsspi_pll &hsspi_pll>;

			clock-names = "hsspi", "pll";

			num-cs = <8>;

			status = "disabled";

		};



		uart0: serial@12000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0x12000 0x1000>;