Commit fa0f4d07 authored by Rob Clark's avatar Rob Clark
Browse files

Merge branch 'msm-fixes' into msm-next 



Back-merge msm-fixes to resolve conflicts.

Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parents d93cf453 1b5d0ddc

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+1 −1
Original line number Diff line number Diff line
@@ -89,7 +89,7 @@ static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit 
			 * since we've already mapped it once in

			 * submit_reloc()

			 */

			if (WARN_ON(!ptr))

			if (WARN_ON(IS_ERR_OR_NULL(ptr)))

				return;



			for (i = 0; i < dwords; i++) {

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h

+1 −1
Original line number Diff line number Diff line
@@ -206,7 +206,7 @@ static const struct a6xx_shader_block { 
	SHADER(A6XX_SP_LB_3_DATA, 0x800),

	SHADER(A6XX_SP_LB_4_DATA, 0x800),

	SHADER(A6XX_SP_LB_5_DATA, 0x200),

	SHADER(A6XX_SP_CB_BINDLESS_DATA, 0x2000),

	SHADER(A6XX_SP_CB_BINDLESS_DATA, 0x800),

	SHADER(A6XX_SP_CB_LEGACY_DATA, 0x280),

	SHADER(A6XX_SP_UAV_DATA, 0x80),

	SHADER(A6XX_SP_INST_TAG, 0x80),

drivers/gpu/drm/msm/adreno/adreno_device.c

+0 −2
Original line number Diff line number Diff line
@@ -369,8 +369,6 @@ static const struct adreno_info gpulist[] = { 
		.hwcg = a640_hwcg,

	}, {

		.rev = ADRENO_REV(6, 9, 0, ANY_ID),

		.revn = 690,

		.name = "A690",

		.fw = {

			[ADRENO_FW_SQE] = "a660_sqe.fw",

			[ADRENO_FW_GMU] = "a690_gmu.bin",

drivers/gpu/drm/msm/adreno/adreno_gpu.h

+8 −4
Original line number Diff line number Diff line
@@ -149,7 +149,8 @@ bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2); 


static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn)

{

	WARN_ON_ONCE(!gpu->revn);

	/* revn can be zero, but if not is set at same time as info */

	WARN_ON_ONCE(!gpu->info);



	return gpu->revn == revn;

}
@@ -161,14 +162,16 @@ static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu) 


static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu)

{

	WARN_ON_ONCE(!gpu->revn);

	/* revn can be zero, but if not is set at same time as info */

	WARN_ON_ONCE(!gpu->info);



	return (gpu->revn < 300);

}



static inline bool adreno_is_a20x(const struct adreno_gpu *gpu)

{

	WARN_ON_ONCE(!gpu->revn);

	/* revn can be zero, but if not is set at same time as info */

	WARN_ON_ONCE(!gpu->info);



	return (gpu->revn < 210);

}
@@ -307,7 +310,8 @@ static inline int adreno_is_a680(const struct adreno_gpu *gpu) 


static inline int adreno_is_a690(const struct adreno_gpu *gpu)

{

	return adreno_is_revn(gpu, 690);

	/* The order of args is important here to handle ANY_ID correctly */

	return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev);

};



/* check for a615, a616, a618, a619 or any derivatives */

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

+7 −1
Original line number Diff line number Diff line
@@ -51,7 +51,7 @@ 


static const u32 fetch_tbl[SSPP_MAX] = {CTL_INVALID_BIT, 16, 17, 18, 19,

	CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, 0,

	1, 2, 3, CTL_INVALID_BIT, CTL_INVALID_BIT};

	1, 2, 3, 4, 5};



static int _mixer_stages(const struct dpu_lm_cfg *mixer, int count,

		enum dpu_lm lm)
@@ -198,6 +198,12 @@ static void dpu_hw_ctl_update_pending_flush_sspp(struct dpu_hw_ctl *ctx, 
	case SSPP_DMA3:

		ctx->pending_flush_mask |= BIT(25);

		break;

	case SSPP_DMA4:

		ctx->pending_flush_mask |= BIT(13);

		break;

	case SSPP_DMA5:

		ctx->pending_flush_mask |= BIT(14);

		break;

	case SSPP_CURSOR0:

		ctx->pending_flush_mask |= BIT(22);

		break;