Commit fafa0cb3 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nv30-nv40/graph: poke zcomp regs from tile_prog hook 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent e1344412

drivers/gpu/drm/nouveau/core/engine/graph/nv20.c

+1 −1
Original line number Diff line number Diff line
@@ -183,7 +183,7 @@ nv20_graph_tile_prog(struct nouveau_engine *engine, int i) 
	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);

	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->addr);



	if (nv_device(engine)->card_type == NV_20) {

	if (nv_device(engine)->chipset != 0x34) {

		nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp);

		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);

		nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->zcomp);

drivers/gpu/drm/nouveau/core/engine/graph/nv40.c

+32 −4
Original line number Diff line number Diff line
@@ -216,10 +216,10 @@ nv40_graph_tile_prog(struct nouveau_engine *engine, int i) 


	switch (nv_device(priv)->chipset) {

	case 0x40:

	case 0x41: /* guess */

	case 0x41:

	case 0x42:

	case 0x43:

	case 0x45: /* guess */

	case 0x45:

	case 0x4e:

		nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);

		nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
@@ -227,6 +227,21 @@ nv40_graph_tile_prog(struct nouveau_engine *engine, int i) 
		nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch);

		nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit);

		nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr);

		switch (nv_device(priv)->chipset) {

		case 0x40:

		case 0x45:

			nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp);

			nv_wr32(priv, NV40_PGRAPH_ZCOMP1(i), tile->zcomp);

			break;

		case 0x41:

		case 0x42:

		case 0x43:

			nv_wr32(priv, NV41_PGRAPH_ZCOMP0(i), tile->zcomp);

			nv_wr32(priv, NV41_PGRAPH_ZCOMP1(i), tile->zcomp);

			break;

		default:

			break;

		}

		break;

	case 0x44:

	case 0x4a:
@@ -235,18 +250,31 @@ nv40_graph_tile_prog(struct nouveau_engine *engine, int i) 
		nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);

		break;

	case 0x46:

	case 0x4c:

	case 0x47:

	case 0x49:

	case 0x4b:

	case 0x4c:

	case 0x63:

	case 0x67:

	default:

	case 0x68:

		nv_wr32(priv, NV47_PGRAPH_TSIZE(i), tile->pitch);

		nv_wr32(priv, NV47_PGRAPH_TLIMIT(i), tile->limit);

		nv_wr32(priv, NV47_PGRAPH_TILE(i), tile->addr);

		nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch);

		nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit);

		nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr);

		switch (nv_device(priv)->chipset) {

		case 0x47:

		case 0x49:

		case 0x4b:

			nv_wr32(priv, NV47_PGRAPH_ZCOMP0(i), tile->zcomp);

			nv_wr32(priv, NV47_PGRAPH_ZCOMP1(i), tile->zcomp);

			break;

		default:

			break;

		}

		break;

	default:

		break;

	}

drivers/gpu/drm/nouveau/core/engine/graph/regs.h

+5 −0
Original line number Diff line number Diff line
@@ -205,6 +205,7 @@ 
#define NV20_PGRAPH_TSIZE(i)                               (0x00400908 + (i*16))

#define NV20_PGRAPH_TSTATUS(i)                             (0x0040090C + (i*16))

#define NV20_PGRAPH_ZCOMP(i)                               (0x00400980 + 4*(i))

#define NV41_PGRAPH_ZCOMP0(i)                              (0x004009c0 + 4*(i))

#define NV10_PGRAPH_TILE(i)                                (0x00400B00 + (i*16))

#define NV10_PGRAPH_TLIMIT(i)                              (0x00400B04 + (i*16))

#define NV10_PGRAPH_TSIZE(i)                               (0x00400B08 + (i*16))
@@ -216,6 +217,7 @@ 
#define NV47_PGRAPH_TSTATUS(i)                             (0x00400D0C + (i*16))

#define NV04_PGRAPH_V_RAM                                  0x00400D40

#define NV04_PGRAPH_W_RAM                                  0x00400D80

#define NV47_PGRAPH_ZCOMP0(i)                              (0x00400e00 + 4*(i))

#define NV10_PGRAPH_COMBINER0_IN_ALPHA                     0x00400E40

#define NV10_PGRAPH_COMBINER1_IN_ALPHA                     0x00400E44

#define NV10_PGRAPH_COMBINER0_IN_RGB                       0x00400E48
@@ -261,9 +263,12 @@ 
#define NV04_PGRAPH_DMA_B_OFFSET                           0x00401098

#define NV04_PGRAPH_DMA_B_SIZE                             0x0040109C

#define NV04_PGRAPH_DMA_B_Y_SIZE                           0x004010A0

#define NV47_PGRAPH_ZCOMP1(i)                              (0x004068c0 + 4*(i))

#define NV40_PGRAPH_TILE1(i)                               (0x00406900 + (i*16))

#define NV40_PGRAPH_TLIMIT1(i)                             (0x00406904 + (i*16))

#define NV40_PGRAPH_TSIZE1(i)                              (0x00406908 + (i*16))

#define NV40_PGRAPH_TSTATUS1(i)                            (0x0040690C + (i*16))

#define NV40_PGRAPH_ZCOMP1(i)                              (0x00406980 + 4*(i))

#define NV41_PGRAPH_ZCOMP1(i)                              (0x004069c0 + 4*(i))



#endif