Commit fcfe0bdc authored by Madhav Chauhan's avatar Madhav Chauhan Committed by Jani Nikula
Browse files

drm/i915/icl: Program DSI Escape clock Divider 



Escape Clock is used for LP communication across the DSI
Link. To achieve the constant frequency of the escape clock
from the variable DPLL frequency output, a variable divider(M)
is needed. This patch programs the same.

v2: (Jani N) Don't end line with "(".

Signed-off-by: default avatarMadhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1530798591-2077-3-git-send-email-madhav.chauhan@intel.com
parent 012bf847

drivers/gpu/drm/i915/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -135,6 +135,7 @@ i915-y += dvo_ch7017.o \ 
	  dvo_ns2501.o \

	  dvo_sil164.o \

	  dvo_tfp410.o \

	  icl_dsi.o \

	  intel_crt.o \

	  intel_ddi.o \

	  intel_dp_aux_backlight.o \

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -9552,6 +9552,7 @@ enum skl_power_gate { 
#define  ICL_BYTE_CLK_PER_ESC_CLK_SHIFT	16

#define  ICL_ESC_CLK_DIV_MASK			0x1ff

#define  ICL_ESC_CLK_DIV_SHIFT			0

#define DSI_MAX_ESC_CLK			20000		/* in KHz */



/* Gen4+ Timestamp and Pipe Frame time stamp registers */

#define GEN4_TIMESTAMP		_MMIO(0x2358)

drivers/gpu/drm/i915/icl_dsi.c

0 → 100644
+64 −0
Original line number Diff line number Diff line 
/*

 * Copyright © 2018 Intel Corporation

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice (including the next

 * paragraph) shall be included in all copies or substantial portions of the

 * Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

 * DEALINGS IN THE SOFTWARE.

 *

 * Authors:

 *   Madhav Chauhan <madhav.chauhan@intel.com>

 *   Jani Nikula <jani.nikula@intel.com>

 */



#include "intel_dsi.h"



static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);

	enum port port;

	u32 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);

	u32 afe_clk_khz; /* 8X Clock */

	u32 esc_clk_div_m;



	afe_clk_khz = DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp,

					intel_dsi->lane_count);



	esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);



	for_each_dsi_port(port, intel_dsi->ports) {

		I915_WRITE(ICL_DSI_ESC_CLK_DIV(port),

			   esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);

		POSTING_READ(ICL_DSI_ESC_CLK_DIV(port));

	}



	for_each_dsi_port(port, intel_dsi->ports) {

		I915_WRITE(ICL_DPHY_ESC_CLK_DIV(port),

			   esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);

		POSTING_READ(ICL_DPHY_ESC_CLK_DIV(port));

	}

}



static void __attribute__((unused))

gen11_dsi_pre_enable(struct intel_encoder *encoder,

		     const struct intel_crtc_state *pipe_config,

		     const struct drm_connector_state *conn_state)

{

	/* step3: enable DSI PLL */

	gen11_dsi_program_esc_clk_div(encoder);

}