Loading sound/soc/codecs/wm8962.c +3 −0 Original line number Diff line number Diff line Loading @@ -1762,6 +1762,9 @@ SND_SOC_BYTES_MASK("3D Coefficients", WM8962_THREED1, 4, WM8962_THREED_ENA), SOC_SINGLE("DF1 Switch", WM8962_DF1, 0, 1, 0), SND_SOC_BYTES_MASK("DF1 Coefficients", WM8962_DF1, 7, WM8962_DF1_ENA), SOC_SINGLE("DRC Switch", WM8962_DRC_1, 0, 1, 0), SND_SOC_BYTES_MASK("DRC Coefficients", WM8962_DRC_1, 5, WM8962_DRC_ENA), WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT), WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT), WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT), Loading Loading
sound/soc/codecs/wm8962.c +3 −0 Original line number Diff line number Diff line Loading @@ -1762,6 +1762,9 @@ SND_SOC_BYTES_MASK("3D Coefficients", WM8962_THREED1, 4, WM8962_THREED_ENA), SOC_SINGLE("DF1 Switch", WM8962_DF1, 0, 1, 0), SND_SOC_BYTES_MASK("DF1 Coefficients", WM8962_DF1, 7, WM8962_DF1_ENA), SOC_SINGLE("DRC Switch", WM8962_DRC_1, 0, 1, 0), SND_SOC_BYTES_MASK("DRC Coefficients", WM8962_DRC_1, 5, WM8962_DRC_ENA), WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT), WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT), WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT), Loading