Commit fe7297bf authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
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arm64: dts: renesas: rzg2lc-smarc-som: Add PHY interrupt support for ETH0 



The PHY interrupt (INT_N) pin is connected to IRQ0 for ETH0.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230712151153.81965-1-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 7a98d75c

arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi

+5 −1
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
 */



#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>

#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>



/ {
@@ -74,6 +75,8 @@ phy0: ethernet-phy@7 { 
		compatible = "ethernet-phy-id0022.1640",

			     "ethernet-phy-ieee802.3-c22";

		reg = <7>;

		interrupt-parent = <&irqc>;

		interrupts = <RZG2L_IRQ0 IRQ_TYPE_LEVEL_LOW>;

		rxc-skew-psec = <2400>;

		txc-skew-psec = <2400>;

		rxdv-skew-psec = <0>;
@@ -121,7 +124,8 @@ eth0_pins: eth0 { 
			 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */

			 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */

			 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */

			 <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */

			 <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */

			 <RZG2L_PORT_PINMUX(0, 0, 1)>;  /* IRQ0 */

	};



	gpio-sd0-pwr-en-hog {