Loading drivers/gpu/drm/nouveau/nouveau_drv.h +0 −5 Original line number Diff line number Diff line Loading @@ -549,11 +549,6 @@ struct nouveau_pm_engine { struct device *hwmon; struct notifier_block acpi_nb; int (*clock_get)(struct drm_device *, u32 id); void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, u32 id, int khz); void (*clock_set)(struct drm_device *, void *); int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); int (*clocks_set)(struct drm_device *, void *); Loading drivers/gpu/drm/nouveau/nouveau_pm.c +8 −54 Original line number Diff line number Diff line Loading @@ -96,31 +96,12 @@ nouveau_pwmfan_set(struct drm_device *dev, int percent) return -ENODEV; } static int nouveau_pm_clock_set(struct drm_device *dev, struct nouveau_pm_level *perflvl, u8 id, u32 khz) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_pm_engine *pm = &dev_priv->engine.pm; void *pre_state; if (khz == 0) return 0; pre_state = pm->clock_pre(dev, perflvl, id, khz); if (IS_ERR(pre_state)) return PTR_ERR(pre_state); if (pre_state) pm->clock_set(dev, pre_state); return 0; } static int nouveau_pm_perflvl_set(struct drm_device *dev, struct nouveau_pm_level *perflvl) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_pm_engine *pm = &dev_priv->engine.pm; void *state; int ret; if (perflvl == pm->cur) Loading @@ -144,18 +125,10 @@ nouveau_pm_perflvl_set(struct drm_device *dev, struct nouveau_pm_level *perflvl) } } if (pm->clocks_pre) { void *state = pm->clocks_pre(dev, perflvl); state = pm->clocks_pre(dev, perflvl); if (IS_ERR(state)) return PTR_ERR(state); pm->clocks_set(dev, state); } else if (pm->clock_set) { nouveau_pm_clock_set(dev, perflvl, PLL_CORE, perflvl->core); nouveau_pm_clock_set(dev, perflvl, PLL_SHADER, perflvl->shader); nouveau_pm_clock_set(dev, perflvl, PLL_MEMORY, perflvl->memory); nouveau_pm_clock_set(dev, perflvl, PLL_VDEC, perflvl->vdec); } pm->cur = perflvl; return 0; Loading Loading @@ -202,28 +175,9 @@ nouveau_pm_perflvl_get(struct drm_device *dev, struct nouveau_pm_level *perflvl) memset(perflvl, 0, sizeof(*perflvl)); if (pm->clocks_get) { ret = pm->clocks_get(dev, perflvl); if (ret) return ret; } else if (pm->clock_get) { ret = pm->clock_get(dev, PLL_CORE); if (ret > 0) perflvl->core = ret; ret = pm->clock_get(dev, PLL_MEMORY); if (ret > 0) perflvl->memory = ret; ret = pm->clock_get(dev, PLL_SHADER); if (ret > 0) perflvl->shader = ret; ret = pm->clock_get(dev, PLL_VDEC); if (ret > 0) perflvl->vdec = ret; } if (pm->voltage.supported && pm->voltage_get) { ret = pm->voltage_get(dev); Loading drivers/gpu/drm/nouveau/nv04_timer.c +2 −1 Original line number Diff line number Diff line Loading @@ -2,6 +2,7 @@ #include "drm.h" #include "nouveau_drv.h" #include "nouveau_drm.h" #include "nouveau_hw.h" int nv04_timer_init(struct drm_device *dev) Loading @@ -17,7 +18,7 @@ nv04_timer_init(struct drm_device *dev) /* determine base clock for timer source */ if (dev_priv->chipset < 0x40) { n = dev_priv->engine.pm.clock_get(dev, PLL_CORE); n = nouveau_hw_get_clock(dev, PLL_CORE); } else if (dev_priv->chipset == 0x40) { /*XXX: figure this out */ Loading Loading
drivers/gpu/drm/nouveau/nouveau_drv.h +0 −5 Original line number Diff line number Diff line Loading @@ -549,11 +549,6 @@ struct nouveau_pm_engine { struct device *hwmon; struct notifier_block acpi_nb; int (*clock_get)(struct drm_device *, u32 id); void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, u32 id, int khz); void (*clock_set)(struct drm_device *, void *); int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); int (*clocks_set)(struct drm_device *, void *); Loading
drivers/gpu/drm/nouveau/nouveau_pm.c +8 −54 Original line number Diff line number Diff line Loading @@ -96,31 +96,12 @@ nouveau_pwmfan_set(struct drm_device *dev, int percent) return -ENODEV; } static int nouveau_pm_clock_set(struct drm_device *dev, struct nouveau_pm_level *perflvl, u8 id, u32 khz) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_pm_engine *pm = &dev_priv->engine.pm; void *pre_state; if (khz == 0) return 0; pre_state = pm->clock_pre(dev, perflvl, id, khz); if (IS_ERR(pre_state)) return PTR_ERR(pre_state); if (pre_state) pm->clock_set(dev, pre_state); return 0; } static int nouveau_pm_perflvl_set(struct drm_device *dev, struct nouveau_pm_level *perflvl) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_pm_engine *pm = &dev_priv->engine.pm; void *state; int ret; if (perflvl == pm->cur) Loading @@ -144,18 +125,10 @@ nouveau_pm_perflvl_set(struct drm_device *dev, struct nouveau_pm_level *perflvl) } } if (pm->clocks_pre) { void *state = pm->clocks_pre(dev, perflvl); state = pm->clocks_pre(dev, perflvl); if (IS_ERR(state)) return PTR_ERR(state); pm->clocks_set(dev, state); } else if (pm->clock_set) { nouveau_pm_clock_set(dev, perflvl, PLL_CORE, perflvl->core); nouveau_pm_clock_set(dev, perflvl, PLL_SHADER, perflvl->shader); nouveau_pm_clock_set(dev, perflvl, PLL_MEMORY, perflvl->memory); nouveau_pm_clock_set(dev, perflvl, PLL_VDEC, perflvl->vdec); } pm->cur = perflvl; return 0; Loading Loading @@ -202,28 +175,9 @@ nouveau_pm_perflvl_get(struct drm_device *dev, struct nouveau_pm_level *perflvl) memset(perflvl, 0, sizeof(*perflvl)); if (pm->clocks_get) { ret = pm->clocks_get(dev, perflvl); if (ret) return ret; } else if (pm->clock_get) { ret = pm->clock_get(dev, PLL_CORE); if (ret > 0) perflvl->core = ret; ret = pm->clock_get(dev, PLL_MEMORY); if (ret > 0) perflvl->memory = ret; ret = pm->clock_get(dev, PLL_SHADER); if (ret > 0) perflvl->shader = ret; ret = pm->clock_get(dev, PLL_VDEC); if (ret > 0) perflvl->vdec = ret; } if (pm->voltage.supported && pm->voltage_get) { ret = pm->voltage_get(dev); Loading
drivers/gpu/drm/nouveau/nv04_timer.c +2 −1 Original line number Diff line number Diff line Loading @@ -2,6 +2,7 @@ #include "drm.h" #include "nouveau_drv.h" #include "nouveau_drm.h" #include "nouveau_hw.h" int nv04_timer_init(struct drm_device *dev) Loading @@ -17,7 +18,7 @@ nv04_timer_init(struct drm_device *dev) /* determine base clock for timer source */ if (dev_priv->chipset < 0x40) { n = dev_priv->engine.pm.clock_get(dev, PLL_CORE); n = nouveau_hw_get_clock(dev, PLL_CORE); } else if (dev_priv->chipset == 0x40) { /*XXX: figure this out */ Loading