Unverified Commit ff6c2269 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v5.19-next-soc' of... 

Merge tag 'v5.19-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers

pmic wrapper:
- code style improvements

devapc:
- add support for MT8186

Smart Voltage Scaling (SVS)
- add support for MT8183 and MT8192

MMSYS:
- Add more display paths for MT8365

Mutex:
- Add common interface for MOD and SOF table
- Add support for MDP on MT8183
- Move binding to soc folder
- Add support to use CMDQ to enable the mutex, needed by MDP3

Power domains:
- Add support for MT6795

* tag 'v5.19-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (29 commits)
  soc: mediatek: mutex: Simplify with devm_platform_get_and_ioremap_resource()
  soc: mediatek: pm-domains: Add support for Helio X10 MT6795
  dt-bindings: power: Add MediaTek Helio X10 MT6795 power domains
  soc: mediatek: SVS: Use DEFINE_SIMPLE_DEV_PM_OPS for svs_pm_ops
  soc: mediatek: mtk-pm-domains: Allow probing vreg supply on two MFGs
  soc: mediatek: fix missing clk_disable_unprepare() on err in svs_resume()
  soc: mediatek: mutex: Use DDP_COMPONENT_DITHER0 mod index for MT8365
  soc: mediatek: mutex: add functions that operate registers by CMDQ
  dt-bindings: soc: mediatek: add gce-client-reg for MUTEX
  dt-bindings: soc: mediatek: move out common module from display folder
  soc: mediatek: mutex: add 8183 MUTEX MOD settings for MDP
  soc: mediatek: mutex: add common interface for modules setting
  soc: mediatek: pm-domains: Add support always on flag
  soc: mediatek: mt8365-mmsys: add DPI/HDMI display path
  soc: mediatek: mutex: add MT8365 support
  soc: mediatek: SVS: add mt8192 SVS GPU driver
  dt-bindings: soc: mediatek: add mt8192 svs dt-bindings
  soc: mediatek: SVS: add debug commands
  soc: mediatek: SVS: add monitor mode
  soc: mediatek: SVS: introduce MTK SVS engine
  ...

Link: https://lore.kernel.org/r/b733bd82-6d99-23ef-0541-98e98eb8d3bc@gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 611f6810 4d3ddc9b

Documentation/devicetree/bindings/power/mediatek,power-controller.yaml

+2 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ properties: 


  compatible:

    enum:

      - mediatek,mt6795-power-controller

      - mediatek,mt8167-power-controller

      - mediatek,mt8173-power-controller

      - mediatek,mt8183-power-controller
@@ -62,6 +63,7 @@ patternProperties: 
      reg:

        description: |

          Power domain index. Valid values are defined in:

              "include/dt-bindings/power/mt6795-power.h" - for MT8167 type power domain.

              "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain.

              "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.

              "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.

Documentation/devicetree/bindings/soc/mediatek/devapc.yaml

+1 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ properties: 
  compatible:

    enum:

      - mediatek,mt6779-devapc

      - mediatek,mt8186-devapc



  reg:

    description: The base address of devapc register bank

Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml→Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml

+13 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#

$id: http://devicetree.org/schemas/soc/mediatek/mediatek,mutex.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Mediatek mutex
@@ -55,6 +55,18 @@ properties: 
      include/dt-bindings/gce/<chip>-gce.h of each chips.

    $ref: /schemas/types.yaml#/definitions/uint32-array



  mediatek,gce-client-reg:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

      items:

        - description: phandle of GCE

        - description: GCE subsys id

        - description: register offset

        - description: register size

    description: The register of client driver can be configured by gce with

      4 arguments defined in this property. Each GCE subsys id is mapping to

      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.



required:

  - compatible

  - reg

Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml

0 → 100644
+91 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/soc/mediatek/mtk-svs.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek Smart Voltage Scaling (SVS) Device Tree Bindings



maintainers:

  - Roger Lu <roger.lu@mediatek.com>

  - Matthias Brugger <matthias.bgg@gmail.com>

  - Kevin Hilman <khilman@kernel.org>



description: |+

  The SVS engine is a piece of hardware which has several

  controllers(banks) for calculating suitable voltage to

  different power domains(CPU/GPU/CCI) according to

  chip process corner, temperatures and other factors. Then DVFS

  driver could apply SVS bank voltage to PMIC/Buck.



properties:

  compatible:

    enum:

      - mediatek,mt8183-svs

      - mediatek,mt8192-svs



  reg:

    maxItems: 1

    description: Address range of the MTK SVS controller.



  interrupts:

    maxItems: 1



  clocks:

    maxItems: 1

    description: Main clock for MTK SVS controller to work.



  clock-names:

    const: main



  nvmem-cells:

    minItems: 1

    description:

      Phandle to the calibration data provided by a nvmem device.

    items:

      - description: SVS efuse for SVS controller

      - description: Thermal efuse for SVS controller



  nvmem-cell-names:

    items:

      - const: svs-calibration-data

      - const: t-calibration-data



  resets:

    maxItems: 1



  reset-names:

    items:

      - const: svs_rst



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names

  - nvmem-cells

  - nvmem-cell-names



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/mt8183-clk.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        svs@1100b000 {

            compatible = "mediatek,mt8183-svs";

            reg = <0 0x1100b000 0 0x1000>;

            interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;

            clocks = <&infracfg CLK_INFRA_THERM>;

            clock-names = "main";

            nvmem-cells = <&svs_calibration>, <&thermal_calibration>;

            nvmem-cell-names = "svs-calibration-data", "t-calibration-data";

        };

    };

drivers/soc/mediatek/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -73,4 +73,14 @@ config MTK_MMSYS 
	  Say yes here to add support for the MediaTek Multimedia

	  Subsystem (MMSYS).



config MTK_SVS

	tristate "MediaTek Smart Voltage Scaling(SVS)"

	depends on MTK_EFUSE && NVMEM

	help

	  The Smart Voltage Scaling(SVS) engine is a piece of hardware

	  which has several controllers(banks) for calculating suitable

	  voltage to different power domains(CPU/GPU/CCI) according to

	  chip process corner, temperatures and other factors. Then DVFS

	  driver could apply SVS bank voltage to PMIC/Buck.



endmenu