Commits · dae847991a4327b8883a2a4e7b0440a42d528b77 · jan.koester / Linux · GitLab

Oct 17, 2012
- drm/i915: add intel_ddi_set_pipe_settings · dae84799
  Paulo Zanoni authored Oct 15, 2012
  dae84799
- drm/i915: add DP support to intel_ddi_enable_pipe_func · 7739c33b
  Paulo Zanoni authored Oct 15, 2012
  7739c33b
- drm/i915: Document the multi-threaded FORCEWAKE bits · c5836c27
  Chris Wilson authored Oct 17, 2012
  c5836c27
- drm/i915: Allow DRM_ROOT_ONLY|DRM_MASTER to submit privileged batchbuffers · d7d4eedd
  Chris Wilson authored Oct 17, 2012
  d7d4eedd
- drm/i915: move hpd handling to (ibx|cpt)_irq_handler · 76e43830
  Daniel Vetter authored Oct 12, 2012
  76e43830
Oct 16, 2012
- drm/i915: Add rc6vids to debugfs · ecd8faea
  Ben Widawsky authored Sep 26, 2012
  ecd8faea
- drm/i915: Workaround to bump rc6 voltage to 450 · 31643d54
  Ben Widawsky authored Sep 26, 2012
  31643d54
- drm/i915: Extract PCU communication · 42c0526c
  Ben Widawsky authored Sep 26, 2012
  42c0526c
Oct 11, 2012
- drm/i915: Fix the SCC/SSC typo in the SPLL bits definition · 39bc66c9
  Damien Lespiau authored Oct 11, 2012
  39bc66c9
Oct 10, 2012
- drm/i915: pipe and planes should be disabled on haswell_crtc_mode_set · 1ce42920
  Paulo Zanoni authored Oct 05, 2012
  1ce42920
- drm/i915: disable DDI_BUF_CTL at the correct time · 2886e93f
  Paulo Zanoni authored Oct 05, 2012
  2886e93f
- drm/i915: don't implement WaDisableEarlyCull for Haswell · 27c6f0a5
  Paulo Zanoni authored Oct 10, 2012
  27c6f0a5
- drm/i915: don't rely on previous values set on DDI_BUF_CTL · 1e6210f4
  Paulo Zanoni authored Oct 05, 2012
  1e6210f4
- drm/i915: completely rewrite the Haswell PLL handling code · 6441ab5f
  Paulo Zanoni authored Oct 05, 2012
  6441ab5f
- drm/i915: add haswell_set_pipeconf · ee2b0b38
  Paulo Zanoni authored Oct 05, 2012
  ee2b0b38
- drm/i915: add proper CPU/PCH checks to crtc_mode_set functions · 5dc5298b
  Paulo Zanoni authored Oct 05, 2012
  5dc5298b
- drm/i915: add haswell_crtc_mode_set · 09b4ddf9
  Paulo Zanoni authored Oct 05, 2012
  09b4ddf9
- drm/i915: enable and disable PIPE_CLK_SEL at the right time · fc914639
  Paulo Zanoni authored Oct 05, 2012
  fc914639
- drm/i915: enable and disable DDI_FUNC_CTL at the right time · 8d9ddbcb
  Paulo Zanoni authored Oct 05, 2012
  8d9ddbcb
- drm/i915: rewrite the LCPLL code · 79f689aa
  Paulo Zanoni authored Oct 05, 2012
  79f689aa
Oct 08, 2012
- drm/i915: Align the retire_requests worker to the nearest second · bcb45086
  Chris Wilson authored Oct 05, 2012
  bcb45086
- drm/i915: Align the hangcheck wakeup to the nearest second · cecc21fe
  Chris Wilson authored Oct 05, 2012
  cecc21fe
- drm/i915: Remove the WaDisableBackToBackFlipFix w/a for Haswell · a9627b88
  Damien Lespiau authored Oct 04, 2012
  a9627b88
- drm/i915: Document that we are implementing WaDisableBackToBackFlipFix · 62cb944f
  Damien Lespiau authored Oct 04, 2012
  62cb944f
Oct 07, 2012
- drm/i915: remove duplicated include from intel_modes.c · 1a4bd9ea
  Wei Yongjun authored Oct 07, 2012
  1a4bd9ea
- drm/i915: Remove the disabling of VHR unit clock gating for HSW · b57a1e96
  Damien Lespiau authored Oct 05, 2012
  b57a1e96
Oct 04, 2012
- drm/i915: implement WaDisableEarlyCull for VLV and IVB · 87f8020e
  Jesse Barnes authored Oct 02, 2012
  87f8020e
- drm/i915: implement WaForceL3Serialization on VLV and IVB · 61939d97
  Jesse Barnes authored Oct 02, 2012
  61939d97
Oct 02, 2012
- drm/i915: s/DRM_IRQ_ARGS/int irq, void *arg · ff1f525e
  Daniel Vetter authored Oct 02, 2012
  ff1f525e
- drm/i915: extract intel_set_pipe_timings from crtc_mode_set · b0e77b9c
  Paulo Zanoni authored Oct 01, 2012
  b0e77b9c
Oct 01, 2012
- drm/i915: add debug logging to ASLE backlight set requests · 749052fb
  Jani Nikula authored Oct 01, 2012
  749052fb
Sep 28, 2012
- drm/i915: Fixup HDMI output on Valleyview · 17dc9257
  Vijay Purushothaman authored Sep 27, 2012
  17dc9257
- drm/i915: Add eDP support for Valleyview · 19c03924
  Gajanan Bhat authored Sep 27, 2012
  19c03924
- drm/i915: Enable DisplayPort in Valleyview · 2a8f64ca
  Vijay Purushothaman authored Sep 27, 2012
  2a8f64ca
- drm/i915: Program correct m n tu register for Valleyview · 74a4dd2e
  Vijay Purushothaman authored Sep 27, 2012
  74a4dd2e
- drm/i915: Add Valleyview lane control definitions · b56747aa
  Vijay Purushothaman authored Sep 27, 2012
  b56747aa
- drm/i915: Fix SDVO IER and status bits for Valleyview · ae33cdcf
  Vijay Purushothaman authored Sep 27, 2012
  ae33cdcf
- drm/i915: Set aux clk to 100MHz for Valleyview · 9473c8f4
  Vijay Purushothaman authored Sep 27, 2012
  9473c8f4
Sep 26, 2012
- drm/i915: limit VLV IRQ enables to those we use · 3bcedbe5
  Jesse Barnes authored Sep 19, 2012
  3bcedbe5
- drm/dp: Make sink count DP 1.2 aware · da131a46
  Adam Jackson authored Sep 20, 2012
  da131a46